Process for fabricating a semiconductor device having a segmented channel region

• US 5,668,021 A
• Filed: 06/04/1996
• Issued: 09/16/1997
• Est. Priority Date: 06/04/1996
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Subramanian, Chitra K., Hayden, James D.
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US08/658,972
• Time in Patent Office: 469 Days
• Field of Search: 437/26, 437/44, 437/45, 437/984
• US Class Current: 438/282
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66583 with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A process for fabricating an MOS device (44) having a segmented channel region (48) includes the fabrication of a compound MOS gate electrode (46). Both the segmented channel region (48) and the MOS gate electrode (46) are formed by creating an opening (18) and an insulating layer (16) overlying a first polycrystalline silicon layer (14). The lateral extent of both the MOS gate electrode (46) and a buried junction region (24) formed in the semiconductor substrate (10) are defined by first sidewall spacer (22) and a second sidewall spacer (32) formed adjacent to the first sidewall spacer (22).

Claims

1. A process for fabricating a semiconductor device comprising the steps of:

providing a semiconductor substrate having a dielectric layer thereon;

forming a first polycrystalline silicon layer overlying the dielectric layer;

forming an insulating layer overlying a first portion and a second portion of the first polycrystalline silicon layer;

forming an opening in the insulating layer exposing the first portion of the first polycrystalline silicon layer, the opening having a wall surface;

forming a first sidewall spacer adjacent to the wall surface;

forming a buried junction region in the semiconductor substrate aligned to the first sidewall spacer;

filling the opening with a second polycrystalline silicon layer;

removing the insulating layer and the second portion of the first polycrystalline silicon layer;

forming a second sidewall spacer adjacent to the first sidewall spacer and overlying the dielectric layer; and

forming source and drain regions in the semiconductor substrate.

2. The process of claim 1, further comprising the step of forming a silicide layer overlying the second polycrystalline silicon layer.

3. The process of claim 1, further comprising the step of doping the semiconductor substrate to form a surface channel region prior to the step of forming the insulating layer.

4. The process of claim 1, further comprising the step of forming lightly doped regions in the semiconductor substrate after removing the second portion of the first polycrystalline silicon layer.

5. The process of claim 1, wherein the step of providing a semiconductor substrate comprises the step of providing a semiconductor substrate of a first conductivity type, and wherein the steps of forming a buried junction region and forming source and drain regions comprise implanting dopants of a second conductivity type.

6. A process for fabricating a semiconductor device comprising the steps of:

providing a semiconductor substrate having a first polycrystalline silicon layer overlying the semiconductor substrate and separated therefrom by a dielectric layer;

forming an insulating layer overlying the first polycrystalline silicon layer;

forming an opening in the insulating layer to define a gate region in the first polycrystalline silicon layer and leaving a remaining portion of the first polycrystalline silicon layer covered by the insulating layer, the opening having a wall surface;

forming a first sidewall spacer in the opening adjacent to the wall surface;

implanting dopants into the semiconductor substrate to form a buried junction region in the semiconductor substrate using the first sidewall spacer as a doping mask;

filling the opening with a second polycrystalline silicon layer;

removing the insulating layer and the remaining portion of the first polycrystalline silicon layer;

forming a second sidewall spacer adjacent to the gate region and to the first sidewall spacer; and

forming source and drain regions in the semiconductor substrate.

7. The process of claim 6, wherein the step of providing a semiconductor substrate comprises the step of providing a semiconductor substrate of a first conductivity type, and wherein the step of implanting dopants comprises implanting dopants of a second conductivity type.

8. The process of claim 6, further comprising the step of forming a silicide layer overlying the second polycrystalline silicon layer.

9. The process of claim 6, wherein the step of forming a first sidewall spacer comprises the steps of depositing a layer of silicon nitride and anisotropically etching the layer of silicon nitride.

10. The process of claim 6, further comprising the step of doping the semiconductor substrate to form a surface channel region prior to the step of forming the insulating layer.

11. A process for fabricating a semiconductor device comprising the steps of:

providing a semiconductor substrate of a first conductivity type having a first polycrystalline silicon layer overlying the semiconductor substrate and separated therefrom by a dielectric layer;

implanting the semiconductor substrate to form a surface channel region of the first conductivity type therein;

forming an insulating layer overlying the first polycrystalline silicon layer;

forming an opening in the insulating layer to define a gate region in the first polycrystalline silicon layer and leaving a remaining portion of the first polycrystalline silicon layer covered by the insulating layer, the opening having a wall surface;

forming a first sidewall spacer in the opening adjacent to the wall surface;

implanting dopants of a second conductivity type into the substrate to form a buried junction region in the substrate using the first sidewall spacer as a doping mask;

filling the opening with a second polycrystalline silicon layer of the second conductivity type;

filling the opening with a second polycrystalline silicon layer;

removing the insulating layer and the remaining portion of the first polycrystalline silicon layer;

forming a second sidewall spacer adjacent to the gate region and to the first sidewall spacer; and

implanting dopants of the second conductivity type into the semiconductor substrate to form source and drain regions using the second sidewall spacer as a doping mask.