DMOS fabrication process implemented with reduced number of masks

• US 5,668,026 A
• Filed: 03/06/1996
• Issued: 09/16/1997
• Est. Priority Date: 03/06/1996
• Status: Expired due to Term

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Megamos Corporation
• Inventors: Hshieh, Fwu-Iuan, So, Koon Chong, Tsui, Yan Man, Lin, True-Lon, Nim, Danny Chi
• Primary Examiner(s): Tsai, Jey
• Assistant Examiner(s): LEBENTRITT, MICHAEL
• Application Number:
  US08/611,745
• Time in Patent Office: 559 Days
• Field of Search: 437/40, 437/41, 437/154, 437/228, 257/335
• US Class Current: 438/272
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A new DMOS fabrication process is disclosed. The fabrication process includes the steps of (a) growing an oxide layer on the substrate; (b) applying a first mask to define an active area and for selectively patterning the oxide layer for keeping a plurality of source implant blocking stumps near a plurality source regions wherein the blocking stumps being formed with width greater than twice a diffusion length of a source dopant and with width less than twice a diffusion length of the body dopant whereby the body regions merging together in the body diffusion becoming a single body region underneath the blocking stumps; (c) applying a second mask for forming a plurality of gates covering a portion of areas between the blocking stumps defining an implant window; (d) implanting a body dopant through the implant window followed by a body diffusion for forming a body region underneath the blocking stumps; (e) implanting the source dopant through the implant window over the source implant blocking stumps following by a source diffusion for forming separate source regions underneath the blocking stumps; (f) depositing an insulating dielectric BPSG/PSG layer; (g) employing a contact mask for etching through the insulating dielectric BPSG/PSG layer and the source implant blocking stumps to define contact windows; (h) depositing a metal layer to form a contact layer through the contact window; and (i) patterning the metal layer with a metal contact to define a plurality of contacts whereby the transistor is fabricated with a four masks process.

Claims

1. A method for fabricating a DMOS transistor supported on a substrate comprising steps of:

(a) growing an oxide layer on said substrate;

(b) applying a first mask for removing said oxide layer to define an active area and for selectively patterning said oxide layer for keeping a plurality of source implant blocking stumps near a plurality of source regions in said substrate wherein said blocking stumps being formed with width greater than twice a diffusion length of a source dopant;

(c) applying a second mask for forming a plurality of gates covering a portion of areas between said blocking stumps thus defining an implant window;

(d) implanting a body dopant through said implant window followed by a body diffusion for forming body regions underneath said blocking stumps wherein said blocking stumps are patterned with width less than twice a diffusion length of said body dopant whereby said body regions merge together in said body diffusion and become a single body region underneath said blocking stumps; and

(e) implanting said source dopant through said implant window over said source implant blocking stumps following by a source diffusion for forming separate source regions underneath said blocking stumps.

2. The method of fabricating said DMOS transistor as recited in claim 1 further comprising steps of:

(f) depositing an insulating dielectric BPSG/PSG layer overlying said plurality of gates;

(g) employing a contact mask for etching through said insulating dielectric BPSG/PSG layer and said source implant blocking stumps to define contact windows;

(h) depositing a metal layer to form a contact layer through said contact window; and

(i) patterning said metal layer with a metal contact to define a plurality of contacts whereby said DMOS transistor is fabricated with a four mask process.

3. The method of fabricating said DMOS transistor as recited in claim 1 wherein:

said step (a) of growing an oxide layer on said substrate is a step of growing said oxide layer with thickness ranging from 10 nm to 10 μ

m.

4. A method for fabricating a DMOS transistor supported on a substrate comprising steps of:

(a) growing an oxide layer on said substrate;

(b) applying a first mask for removing said oxide layer to define an active area and for selectively patterning said oxide layer for keeping a plurality of source implant blocking stumps near a plurality of source regions in said substrate wherein said blocking stumps being formed with width greater than twice a diffusion length of a source dopant;

(c) applying a trench mask to form a plurality of trenches on said substrate between said blocking stumps followed by forming a plurality of gates in said trenches;

(d) implanting a body dopant through said implant window followed by a body diffusion for forming body regions underneath said blocking stumps wherein said blocking stumps are patterned with width less than twice a diffusion length of said body dopant whereby said body regions merge together in said body diffusion and become a single body region underneath said blocking stumps; and

(e) implanting said source dopant through said implant window over said source implant blocking stumps following by a source diffusion for forming separate source regions underneath said blocking stumps;

applying a trench mask to form a plurality of trenches on substrate between said blocking stumps followed by forming a plurality of gates in said trenches.

5. A method for fabricating a trenched DMOS transistor supported on a substrate comprising steps of:

(a) growing an oxide layer on said substrate;

(b) applying a first mask for removing said oxide layer to define an active area and for selectively patterning said oxide layer for keeping a plurality of source implant blocking stumps near a plurality of source regions in said substrate wherein said blocking stumps being formed with width greater than twice a diffusion length of a source dopant;

(c) applying a second mask for forming a plurality of trenches between said blocking stumps and forming gates in said trenches thus defining a plurality of implant windows between said gates and said blocking stumps;

(d) implanting a body dopant through said implant windows followed by a body diffusion for forming body regions underneath said blocking stumps; and

(e) implanting said source dopant through said implant windows over said source implant blocking stumps following by a source diffusion for forming separate source regions underneath said blocking stumps.

6. The method of fabricating said trenched DMOS transistor as recited in claim 5 wherein:

said step (b) of applying said first mask for selectively patterning said oxide layer for keeping a plurality of source implant blocking stumps near a plurality of source regions is a step of patterning said blocking stumps with width less than twice a diffusion length of said body dopant whereby said body regions merge together in said body regions and become a single body region underneath said blocking stumps.

7. The method of fabricating said trenched DMOS transistor as recited in claim 6 further comprising steps of:

(f) depositing an insulating dielectric BPSG/PSG layer;

(g) employing a contact mask for etching through said insulating dielectric BPSG/PSG layer and said source implant blocking stumps to define contact windows;

(h) depositing a metal layer to form a contact layer through said contact window; and

(i) patterning said metal layer with a metal contact to define a plurality of contacts whereby said DMOS transistor is fabricated with a four mask process.