Method for manufacturing a semiconductor acceleration sensor device

• US 5,668,033 A
• Filed: 05/17/1996
• Issued: 09/16/1997
• Est. Priority Date: 05/18/1995
• Status: Expired due to Term

• Current Assignee: Nippondenso Co., Ltd. (DENSO Corporation)
• Original Assignee: Nippondenso Co., Ltd. (DENSO Corporation)
• Inventors: Kanamori, Katuhiko, Kurahashi, Takashi, Yoshihara, Shinji, Ohara, Fumio
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US08/648,968
• Time in Patent Office: 487 Days
• Field of Search: 437/51, 437/226, 437/227, 437/901, 437/927, 437/974, 148/DIG. 12, 148/DIG. 28
• US Class Current: 438/113
• CPC Class Codes: B29C 2043/023 having a plurality of grooves
• CPC Class Codes: B29C 33/0022 Multi-cavity moulds B29C33/301 takes precedence
• CPC Class Codes: B29C 43/36 Moulds for making articles of definite length, i.e. discrete articles
• CPC Class Codes: B81B 2207/093 Conductive package seal
• CPC Class Codes: B81C 1/00301 Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
• CPC Class Codes: B81C 1/00865 Multistep processes for the separation of wafers into individual elements
• CPC Class Codes: G01P 1/023 for acceleration measuring devices
• CPC Class Codes: G01P 15/0802 Details
• CPC Class Codes: G01P 15/124 by semiconductor devices comprising at least one PN junction, e.g. transistors
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 23/053 the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01068 : Erbium [Er]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/16235 : Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: Y10S 148/012 : Bonding, e.g. electrostatic for strain gauges

Abstract

On a silicon wafer there is formed a movable gate MOS transistor (sensing element: functional element). A bonding frame consisting of a silicon thin film is patterned around an element formation region on the surface of the silicon wafer. On a cap forming silicon wafer there is projectively provided a leg portion on the bottom surface of which a bonding layer consisting of a gold film is formed. The cap forming silicon wafer is disposed on the silicon wafer, whereupon heating with respect thereto is performed at a temperature equal to higher than a gold/silicon eutectic temperature to thereby make bondage between the bonding frame of the silicon wafer and the bonding layer of the cap forming silicon wafer. Thereafter, the both wafers are diced in chip units.

Claims

1. A method for manufacturing a semiconductor device including a semiconductor wafer having a functional element formed on a surface thereof and a cap covering the functional element with a spatial portion being provided with respect to this functional element on the surface of the semiconductor wafer, comprising:

a functional element forming step of forming a plurality of functional elements on the semiconductor wafer for the formation of the functional elements and forming pads for making wire connection between each functional element and the outside, between the functional element and a predetermined position of the semiconductor wafer at which this semiconductor wafer is to be divided;

a bonding frame forming step of forming a bonding frame surrounding each functional element in a region around each functional element on the surface of the semiconductor wafer and on a side nearer to the functional element than to the pad;

a bonding step of bonding a cap forming wafer having a leg portion at a position corresponding to the bonding frame, onto the semiconductor wafer by making bondage between the leg portion and the bonding frame; and

a cutting step of cutting the semiconductor wafer at the predetermined position thereof at which this semiconductor wafer is to be divided and also cutting the cap forming wafer at a cutting position on a side nearer to the bonding frame than to the position of the cap forming wafer that opposes the pad.

2. A method as set forth in claim 1, wherein:

the cutting step is to cut simultaneously the predetermined position of the semiconductor wafer at which this semiconductor wafer is to be divided and the position of the cap forming wafer that opposes the predetermined position of the semiconductor wafer, and

thereafter to cut the cutting position of the cap forming wafer.

3. A method as set forth in claim 1, wherein:

the cutting step is to cut the cutting position of the cap forming wafer; and

thereafter to cut the predetermined position of the semiconductor wafer at which this semiconductor wafer is to be divided.

4. A method as set forth in claim 1, in which the bonding frame consists of a material containing silicon (Si);

and which further comprises a bonding layer forming step of forming a bonding layer consisting of a material containing a gold (Au) onto the leg portion; and

wherein

the bonding step is to heating up to a temperature higher than a gold (Au)/silicon (Si) eutectic temperature in a state wherein the bonding frame of the semiconductor wafer and the cap forming wafer are in contact with each other to thereby bond the bonding frame of the semiconductor wafer and the bonding layer of the cap forming wafer.

5. A method as set forth in claim 4, further comprising a step of disposing as an electromagnetic shielding layer a gold (Au) layer becoming the bonding layer on the inner surface of the cap.

6. A method as set forth in claim 4, wherein the functional element includes a movable gate electrode having a bridged beam structure, the movable gate electrode consisting of a silicon thin film, and a fixed source electrode and fixed drain electrode formed in the semiconductor wafer;

and the movable gate electrode and the bonding frame are formed simultaneously.

7. A method as set forth in claim 4, wherein a film capable of forming an eutectic material at a temperature lower than a gold (Au)/silicon (Si) eutectic temperature is disposed on the surface of the bonding layer of the cap forming wafer;

and the bonding step is to bond the bonding frame of the semiconductor wafer and the bonding layer of the cap forming wafer through the intermediary of this film.

8. A method as set forth in claim 4, wherein:

the bonding frame forming step comprises a step of sequentially forming a metal film capable of reducing a silicon oxide film and an anti-oxidation film capable of preventing oxidation of the metal film on the surface of the bonding layer of the cap forming wafer; and

the bonding step is to bond the bonding frame of the semiconductor wafer and the bonding layer of the cap forming wafer with the metal film and the anti-oxidation film intervening therebetween.

9. A method as set forth in claim 1, further comprising steps of adhering the cap forming wafer to a wafer support member, making cuts for the division and formation of the cap forming wafer into caps in chip units, bonding the cap forming wafer and the semiconductor wafer, and thereafter separating the wafer support member from the cap forming wafer to thereby remove unnecessary portions of the cap forming wafer.

10. A method as set forth in claim 1, wherein the bonding step is performed in an atmosphere of vacuum or inert gas or under a prescribed level of pressure to thereby make the interior of the cap have an atmosphere of vacuum or inert gas or a prescribed level of pressure.

11. A method as set forth in claim 1, wherein cutting of the semiconductor wafer at the predetermined position where this semiconductor wafer is to be divided and cutting of the cap forming wafer are both performed by a cutter being applied thereto from a side of the cap forming wafer.

12. A method for manufacturing a semiconductor device including a semiconductor wafer having a functional element formed on a surface thereof and a cap covering the functional element with a spatial portion being provided with respect to this functional element on the surface of the semiconductor wafer, comprising:

a functional element forming step of forming a plurality of functional elements on the semiconductor wafer for the formation of the functional elements;

a bonding frame forming step of forming a bonding frame in a region surrounding each functional element on the surface of the semiconductor wafer and on a side nearer by a prescribed distance to the functional element than to the predetermined position of the semiconductor wafer at which this semiconductor wafer is to be divided;

a bonding step of bonding a cap forming wafer having a leg portion at a position corresponding to the bonding frame pattern, onto the semiconductor wafer by making bondage between the leg portion and the bonding frame; and

a cutting step of cutting the semiconductor wafer at the predetermined position thereof at which this semiconductor wafer is to be divided and also cutting the cap forming wafer at a cutting position on a side nearer to the bonding frame than to the position of the cap forming wafer that opposes the predetermined position of the semiconductor wafer at which this semiconductor wafer is to be divided.

13. A method for manufacturing a semiconductor device including a semiconductor wafer having a functional element formed on a surface thereof and a cap covering the functional element with a spatial portion being provided with respect to this functional element on the surface of the semiconductor wafer, comprising:

a first step of patterning a bonding frame consisting of a silicon thin film around a region for the formation of the functional element on a surface of the semiconductor wafer for the formation of the functional element and patterning a bonding layer consisting of a gold (Au) film at a position of the cap forming wafer that corresponds to the bonding frame pattern;

a second step of heating up to a temperature higher than a gold/silicon eutectic temperature in a state wherein the bonding frame of the semiconductor wafer and the bonding layer of the cap forming wafer are in contact with each other to thereby bond the bonding frame of the semiconductor wafer and the bonding layer of the cap forming wafer; and

a third step of dicing the semiconductor wafer in chip units.

14. A method as set forth in claim 13, wherein the cap has a leg portion at a position corresponding to a region surrounding the functional element formation region;

and the cap forming wafer in the second step has the bonding layer formed at a forward end surface of the leg portion.

15. A method as set forth in claim 13, further comprising a step of disposing the gold film becoming the bonding layer on an inner surface of the cap as an electromagnetic shielding layer.

16. A method as set forth in claim 13, in which the functional element includes a bridged beam structure of movable gate electrode consisting of a silicon thin film, a fixed source electrode and a fixed drain electrode, and which further comprises a step of forming the bonding frame simultaneously with the formation of the movable gate electrode.

17. A method as set forth in claim 13, wherein a film capable of forming an eutectic material at a temperature lower than a gold/silicon eutectic temperature is disposed on the surface of the bonding layer of the cap forming wafer;

and the second step comprises a step of bonding the bonding frame of the semiconductor wafer and the bonding layer of the cap forming wafer through the intermediary of this film.

18. A method as set forth in claim 13, wherein the second step comprises a step of providing a metal anti-diffusion layer between the cap forming wafer consisting of silicon and the bonding layer and thereafter making bondage between the bonding frame of the semiconductor wafer and the bonding layer of the cap forming wafer.

19. A method as set forth in claim 13, further comprising steps of adhering the cap forming wafer to a wafer support member, making cuts for the division and formation of the cap forming wafer into caps in chip units, bonding the cap forming wafer and the semiconductor wafer, and thereafter separating the wafer support member from the cap forming wafer to thereby remove unnecessary portions of the cap forming wafer.

20. A method as set forth in claim 13, wherein wafer bonding in the second step is performed in an atmosphere of vacuum or inert gas or under a prescribed level of pressure to thereby make the interior of the cap have an atmosphere of vacuum or inert gas or a prescribed level of pressure.