Process for fabricating a high voltage MOS transistor for flash EEPROM applications having a uni-sided lightly doped drain

• US 5,668,034 A
• Filed: 05/14/1996
• Issued: 09/16/1997
• Est. Priority Date: 12/06/1991
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Sery, George E., Smudski, Jan A.
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US08/645,691
• Time in Patent Office: 490 Days
• Field of Search: 437/52, 437/47, 437/979, 437/40 AS, 437/41 AS, 437/41 RLD, 437/59, 148/DIG. 109, 148/DIG. 163
• US Class Current: 438/266
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/44 with a control gate layer also being used as part of the peripheral transistor
• CPC Class Codes: H10B 41/48 with a tunnel dielectric layer also being used as part of the peripheral transistor
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor
• CPC Class Codes: Y10S 438/974 Substrate surface preparation
• CPC Class Codes: Y10S 438/981 Utilizing varying dielectric thickness

Abstract

High voltage MOS transistors are fabricated contemporaneously with scaled flash EEPROM array transistors. Active silicon regions separated by field oxide isolation structures are formed as in the prior art. A sacrificial thermal oxide layer simultaneously removes Kooi effect residual nitridization and provides gate oxide for the high voltage transistors of a thickness commensurate with the high voltage application. The sacrificial oxide is thereafter removed from all circuit areas except over high voltage device active areas. Growth of tunnel oxide, first polysilicon, interpoly dielectric, peripheral gate oxide and second polysilicon layers as well as patterning of the layers are accomplished in a known manner. The second polysilicon layer is patterned to create lines which lie within lines formed of the first polysilicon layer, the second polysilicon layer aiding controlling the final channel length of the high voltage devices. A uni-sided lightly doped drain structure is created in n-channel enhancement and intrinsic high voltage devices only by an appropriately shaped mask to block the n+ source-drain implant over a previously implanted tip region disposed between the gate and drain, thereby minimizing hot-carrier effects in the drains. Metallization for the high voltage transistors is made over field oxide to the polysilicon control gates formed from the first polysilicon layer.

Claims

1. A process for fabricating a memory circuit, said circuit comprising high voltage transistors, array transistors and peripheral transistors, said process comprising:

a. forming a high voltage transistor in said process comprising the steps of;

forming a high voltage transistor active region of a first conductivity type on a silicon substrate;

forming a high voltage transistor gate insulator comprising a first oxide layer on said high voltage transistor active region;

forming a high voltage transistor control gate above said high voltage transistor gate insulator comprising a first conductive layer;

forming a first masking member above said high voltage transistor control gate;

performing a first implant of a second conductivity type, said first implant being aligned with said masking member to form a source, a drain, and a channel region there between;

forming a second masking member, said second masking member disposed above at least a portion of said first masking member and at least a portion of said drain; and

,

performing a second implant of said second conductivity type of form a source subregion within said source and a drain subregion within said drain, of dopant than said source and said subregion having a greater concentration being aligned with said high voltage transistor control gate, said drain subregion spaced a distance from being aligned with said high voltage transistor control gate;

b. forming an array transistor in an array active region formed on said silicon substrate, said array transistor having an array transistor source, an array transistor drain and an array transistor gate; and

c. forming a peripheral transistor in a peripheral transistor active region formed on said silicon substrate, said peripheral transistor having a peripheral transistor source, a peripheral transistor drain and a peripheral transistor gate;

wherein said process contemporaneously forms said high voltage transistors, said array transistors, and said peripheral transistors.

2. The method as described in claim 1 wherein said array transistor gate comprises a floating gate formed over said array active region, and wherein said high voltage transistor control gate and said floating gate of said array transistor are formed contemporaneously and comprise a first conductive layer.

3. The method as described in claim 1 wherein said step of forming said array transistor comprises forming an array control gate over said array active region, and wherein said first masking member and said array control gate of said array transistor are formed contemporaneously and comprise a second conductive layer.

4. The method as described in claim 1 wherein said step of forming said array transistor comprises forming an array control gate over said array active region, and wherein said first masking member and said array control gate of said array transistor are formed contemporaneously and comprise a second conductive layer.

5. The method as described in claim 4 wherein said first conductive layer comprises polysilicon and said second conductive layer comprises polysilicon.

6. The method as described in claim 1 wherein said first implant is performed using phosphorous and said second implant is performed using arsenic.

7. The method as described in claim 2 wherein said first implant is performed using phosphorous and said second implant is performed using arsenic.

8. The method as described in claim 3 wherein said first implant is performed using phosphorous and said second implant is performed using arsenic.

9. The method as described in claim 1 wherein said step of forming said peripheral transistor further comprises the steps of forming an insulative layer above said high voltage transistor control gate and below said first masking member, and forming a peripheral transistor gate insulator on said peripheral transistor active region comprising said insulative layer.

10. The method as described in claim 2 wherein said step of forming said peripheral transistor further comprises the steps of forming an insulative layer above said high voltage transistor control gate and below said first masking member, and forming a peripheral transistor gate insulator on said peripheral transistor active region comprising said insulative layer.

11. The method as described in claim 3 wherein said step of forming said peripheral transistor further comprises the steps of forming an insulative layer above said high voltage transistor control gate and below said first masking member, and forming a peripheral transistor gate insulator on said peripheral transistor active region comprising said insulative layer.

12. The method as described in claim 1 wherein said first oxide layer is deposited to a thickness of approximately 350 Å

.

13. The method as described in claim 1 wherein said first oxide layer is additionally formed on said array transistor active region and wherein said method further comprises the step of removing said first oxide layer from said array transistor active region.

14. The method as described in claim 12 wherein said first oxide layer is additionally formed on said array transistor active region and wherein said method further comprises the step of removing said first oxide layer from said array transistor active region.