Method of planarizing a layer of material

• US 5,668,063 A
• Filed: 05/23/1995
• Issued: 09/16/1997
• Est. Priority Date: 05/23/1995
• Status: Expired due to Fees

• Current Assignee: Silicon Valley Group Thermal Systems LLC (ASML Holding NV)
• Original Assignee: Watkins Johnson Co. (Qorvo, Inc.)
• Inventors: Lightfoot, Kurt James, Fry, Howard Wallace
• Primary Examiner(s): CHU, JOHN S Y
• Application Number:
  US08/447,809
• Time in Patent Office: 847 Days
• Field of Search: 437/228, 437/228 PL, 437/228 ES, 437/7, 437/231, 437/235, 156/626.1, 156/636.1, 156/653.1
• US Class Current: 438/5
• CPC Class Codes: B24B 37/013 Devices or means for detecting lapping completion
• CPC Class Codes: H01L 21/31051 Planarisation of the insulating layers H01L21/31058 takes precedence
• CPC Class Codes: H01L 22/26 Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement endpoint detection arrangements in CMP apparatus B24B37/013, in discharge apparatus H01J37/32

Abstract

A method of planarizing a layer of material having a pre-determined thickness above a circuit feature on a semiconductor device is provided. A first layer of material is formed atop the surface of the semiconductor substrate and circuit feature to a pre-determined thickness. A thin, continuous trace layer of doped silicon oxide material is formed atop the first layer, and then a second layer of material is formed atop the trace layer. The second layer is planarized, and planarization is terminated upon reaching the trace layer, thereby providing a semiconductor with a planar layer.

Claims

1. A method of forming a planar layer having a predetermined thickness above a circuit feature of a semiconductor device comprising the steps of:

forming a first layer of a first material atop a surface of a semiconductor substrate and circuit feature with said predetermined thickness above said circuit feature;

forming in one fabrication step, a thin continuous trace layer of a doped silicon oxide material on the entire surface of said first layer;

forming a second layer of material on said trace layer;

planarizing said second layer by removing portions of said second layer;

detecting when the removal of said second layer reaches a portion of said trace layer; and

terminating planarization upon detection of said portion of said trace layer whereby the resulting layer is planar having said pre-determined thickness above said circuit features.

2. The method of claim 1 wherein said second layer is the same material as said first layer.

3. The method of claim 1 wherein detection of a portion of said trace layer is by detecting the chemical species of said trace layer.

4. The method of claim 1 wherein the planarization step further comprises:

chemical mechanical polishing said second layer with a slurry, said slurry exhibiting a chemical characteristic; and

during polishing detecting the chemical characteristic of said slurry and observing a noticeable change in said chemical characteristic when a portion of said trace layer becomes exposed to said slurry.

5. The method of claim 1 wherein said trace layer exhibits conductivity, and detection of a portion of said trace layer is by detecting the conductivity of said trace layer.

6. The method of claim 1 wherein said trace layer is borosilicate glass.

7. The method of claim 1 wherein said trace layer is phosphosilicate glass.

8. The method of claim 1 wherein said trace layer is arsenosilicate glass.

9. The method of claim 1 wherein said trace layer is borophosphosilicate glass.

10. A method of forming a planar layer having a predetermined thickness above a circuit feature of a semiconductor device comprising the steps of:

(a) forming a first layer of a first a material atop a surface of a semiconductor substrate and circuit feature with said predetermined thickness above said circuit feature;

(b) forming in one fabrication step, a thin continuous trace layer of a doped silicon oxide material on the entire surface of said first layer;

(c) forming a second layer of material on said trace layer;

(d) planarizing said second layer by removing portions of said second layer;

(e) detecting when the removal of said second layer reaches a portion of said trace layer;

(f) terminating planarization upon detection of said portion of said trace layer whereby the resulting layer is planar having said pre-determined thickness above said circuit features; and

(g) repeating steps (a), (b), (c), (d), (e), and (f) in sequence N times, where N is an integer and N is greater than, or equal to, 1.

11. The method of claim 10 wherein said second layer is the same material as said first layer.

12. The method of claim 10 wherein said first layer in repetitive step (g) is a different material from said first layer in step (a).

13. The method of claim 10 wherein said trace layer in repetitive step (g) is a different material from said trace layer in step (b).

14. The method of claim 10 wherein said second layer in repetitive step (g) is a different material from said second layer in step (c).

15. The method of claim 10 wherein detection of a portion of said trace layers during the repetitive sequences is by detecting the chemical species of said trace layer.

16. The method of claim 10 wherein the planarization steps further comprises:

chemical mechanical polishing said second layers during the repetitive sequences with a slurry, said slurry exhibiting a chemical characteristic; and

during polishing detecting the chemical characteristic of said slurry and observing a noticeable change in said chemical characteristic during each repetitive sequence when a portion of said trace layer becomes exposed to said slurry.

17. The method of claim 10 wherein said trace layers exhibit conductivity, and detection of a portion of said trace layer is by detecting the conductivity of said trace layer.

18. The method of claim 10 wherein said trace layer are borosilicate glass.

19. The method of claim 10 wherein said trace layer are phosphosilicate glass.

20. The method of claim 10 wherein said trace layer are arsenosilicate glass.

21. The method of claim 10 wherein said trace layer are borophosphosilicate glass.