Memory management for an MPEG2 compliant decoder

• US 5,668,599 A
• Filed: 03/19/1996
• Issued: 09/16/1997
• Est. Priority Date: 03/19/1996
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Herndon, Steven Bradford, Myers, John David, Ngai, Chuck Hong, Ciacelli, Mark Louis, Cheney, Dennis Phillip
• Primary Examiner(s): Chin, Tommy P.
• Assistant Examiner(s): DIN, LUANNE PAN
• Application Number:
  US08/618,660
• Time in Patent Office: 546 Days
• Field of Search: 348/402, 348/409, 348/415, 348/416, 348/399, 370/60
• US Class Current: 375/240.15
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/427 Display on the fly, e.g. simultaneous writing to and reading from decoding memory
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/4305 Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/44004 involving video buffer management, e.g. video decoder buffer or video display buffer
• CPC Class Codes: H04N 5/907 using static stores, e.g. storage tubes or semiconductor memories H04N5/91 takes precedence

Abstract

Disclosed is a digital signal decoder system for receiving compressed encoded digitized video signals and transmitting decompressed decoded digital video signals. This is accomplished with a minimum of DRAM demand through the use of a Spill Buffer.

Claims

1. A digital video decoder comprising an input data buffer, a variable length decoder, a dequantizer, an inverse discrete cosine transform decoder, a motion compensator, and a frame memory, said frame memory having at least a past reference frame buffer, a future reference frame buffer, a frame buffer for a frame currently being decoded, and a Spill Buffer, said Spill Buffer being dynamically allocable within said frame memory as frames are decoded, and where said three frame buffers are accessed on a rotating basis according to the following algorithm:

C=D*NBF+ NBF*(T*(PREV =B)+P*(PREV=B*PRES =B));

P=C*NBF+ NBF*F*(PRES =B);

F=T*(PREV =B*PRES= B)+P*(PREV=B*PRES =B);

D=C*NBF+ NBF*(F*(PRES =B)+T*(PREV =B*PRES=B)); and

T=D;

where

C=Current picture pointer;

P=Past picture pointer;

F=Future picture pointer;

D=Display picture pointer;

T=Temporary pointer;

PRES=Present picture type;

PREV=Previous picture type; and

NBF=No B frame mode.

2. The digital video decoder of claim 1 wherein the three frame buffers are each large enough to hold a decoded frame.

3. The digital video decoder of claim 1 wherein a picture being displayed comes from either the past reference frame buffer for an I- or P- picture, or from the current frame buffer for a B- picture.

4. The digital video decoder of claim 1 wherein said decoder supports normal mode decoding and low delay mode decoding.

5. The digital video decoder of claim 4 wherein said decoder supports normal mode decoding and wherein said frame buffer memory is allocated at between 2 and 4 MBytes with an 8 byte data bus.

6. The digital video decoder of claim 4 wherein said decoder supports low mode decoding and said frame buffer memory is allocated at 1 MByte with a 4 byte data bus.

7. A method of decoding a digital video datastream in a digital video decoder comprising an input data buffer, a variable length decoder, a dequantizer, an inverse discrete cosine transform decoder, a motion compensator, and a frame memory, said frame memory having at least a past reference frame buffer, a future reference frame buffer, a frame buffer for a frame currently being decoded, and a Spill Buffer, said Spill Buffer being dynamically allocable within said frame memory as frames are decoded, and where said three frame buffers are accessed on a rotating basis according to the following algorithm:

C=D*NBF+ NBF*(T*(PREV =B)+P*(PREV=B*PRES =B));

P=C*NBF+ NBF*F*(PRES =B);

F=T*(PREV =B*PRES= B)+P*(PREV=B*PRES =B);

D=C*NBF+ NBF*(F*(PRES =B)+T*(PREV =B*PRES=B)); and

T=D;

where

C=Current picture pointer;

P=Past picture pointer;

F=Future picture pointer;

D=Display picture pointer;

T=Temporary pointer;

PRES=Present picture type;

PREV=Previous picture type; and

NBF=No B frame mode;

which method comprises;

a. storing a frame currently being decoded in the current frame buffer;

b. storing a past reference frame in the past reference frame buffer; and

c. storing a future reference frame in the future reference frame buffer.

8. The method of claim 7 comprising storing a complete frame in each of said frame buffers.

9. The method of claim 7 wherein a picture being displayed comes from either the past reference frame buffer for an I- or P- picture, or from the current frame buffer for a B- picture.

10. The method of claim 7 comprising assigning the Spill Buffer dynamically while decoding a picture.

11. The method of claim 10 comprising dynamically assigning the Spill Buffer to one of the three frame buffers.

12. The method of claim 7 further comprising seamless sequence switching.