Synchronous burst extended data out DRAM

• US 5,668,773 A
• Filed: 11/02/1995
• Issued: 09/16/1997
• Est. Priority Date: 12/23/1994
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Merritt, Todd, Manning, Troy A., Zagar, Paul S.
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US08/552,199
• Time in Patent Office: 684 Days
• Field of Search: 365/233.5, 365/238.5, 365/239, 365/235, 365/236
• US Class Current: 365/233.1
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1024 Extended data output [EDO] mode, i.e. keeping output buffer enabled during an extended period of time
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers

Abstract

An integrated circuit memory device is described which can operate at high data speeds. The memory device can either store or retrieve data from the memory in a burst access operation. The burst operations latches a memory address from external address lines and internally generates additioned memory addresses. A clock signed is provided to synchronize the burst operations. The clock signed is independent of an address latch signal used to latch an external address.

Claims

1. A memory device comprising:

a plurality of addressable memory elements; and

addressing circuitry adapted to receive a first memory element address in response to a transition of a clock signal and an address latch signal, and further adapted to generate a second memory element address in response to a subsequent transition of the clock signal,

wherein the clock signal is provided on an output enable input.

2. A synchronous memory device comprising:

a memory array having a plurality of addressable memory elements;

a plurality of address inputs for receiving memory element addresses;

an address latch input for receiving an address latch signal;

an address latch for receiving a first memory element address in response to a transition of a clock signal and the address latch signal; and

an address generation circuit responsive to successive transitions of the clock signal and to the first memory element address for generating additional memory element addresses,

wherein the clock signal is provided on an output enable input.