High speed mask register for a configurable cellular array

• US 5,670,897 A
• Filed: 08/27/1996
• Issued: 09/23/1997
• Est. Priority Date: 11/05/1992
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Kean, Thomas A.
• Primary Examiner(s): Hudspeth, David R.
• Application Number:
  US08/711,225
• Time in Patent Office: 392 Days
• Field of Search: 326/39-41, 326/44
• US Class Current: 326/41
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17752 for hot reconfiguration
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration
• CPC Class Codes: H03K 19/17758 for speeding up configuration or reconfiguration

Abstract

An field programmable gate array (FPGA) of cells arranged in rows and columns is interconnected by a hierarchical routing structure. Switches separate the cells into blocks and into blocks of blocks with routing lines interconnecting the switches to form the hierarchy. Also, select units for allowing memory bits to be addressed both individually and in large and arbitrary groups are disclosed. Further a control store for configuring the FPGA is addressed as an SRAM and can be dynamically reconfigured during operation.

Claims

1. A register structure comprising:

a plurality of input lines;

a mask register having one bit for each input line;

a plurality of output lines;

a matrix of programmable connectors for programmably connecting each of said input lines to each of said output lines;

for each of said programmable connectors, a decoder receiving an enable signal from a corresponding bit in said mask register and a decode address signal derived from all less significant bits in said mask register, each of said decoders enabling a corresponding input line to be connected to a corresponding output line only when said decode address signal indicates that no previous input lines have been connected to that output line.

2. A register structure as in claim 1 further comprising for each mask register bit an increment register for generating said decode address.

3. A register structure comprising:

a plurality of input lines;

a mask register having one bit for each input line;

a plurality of output lines;

a matrix of programmable connectors for programmably connecting each of said input lines to each of said output lines;

for each of said programmable connectors, a decoder receiving an enable signal from a corresponding bit in said mask register and a decode address signal derived from all more significant bits in said mask register, each of said decoders enabling a corresponding input line to be connected to a corresponding output line only when said decode address signal indicates that no previous input lines have been connected to that output line.