Spatial light modulator having redundant memory cells

• US 5,670,976 A
• Filed: 02/28/1995
• Issued: 09/23/1997
• Est. Priority Date: 02/28/1995
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Honzawa, Takeshi, Numaga, Shigeki, Chiu, Edison H.
• Primary Examiner(s): Faile, Andrew
• Assistant Examiner(s): CHRISTENSEN, ANDREW BRUCE
• Application Number:
  US08/395,545
• Time in Patent Office: 938 Days
• Field of Search: 345/84, 345/93, 345/190, 345/200, 345/85, 348/571, 348/771, 365/200, 371/10.3
• US Class Current: 345/84
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2330/08 Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared
• CPC Class Codes: G09G 3/34 by control of light from an independent source
• CPC Class Codes: H04N 9/30 using solid-state colour display devices

Abstract

A spatial light modulator (10) of the DMD type having an array of memory cells (16) controlling an array of pixels (12). The memory cell array (16) has several integral, interleaved spare rows of memory cells MR (R1), MR (R2), and MR (R3), which can be selectively utilized to replace a defective row of primary memory cells. A fused row address mapping logic circuit (40) includes a network of fuses (F0-F12) and controls the implementation of memory cells, as well as the mapping of address signals to the memory cells as a function of inputs (R0-R11) received from a row decoder circuit (20). This circuit (40) is transparent to the row address decoder circuit (20). The present invention is suitable for large spatial light modulators compatible with high definition television (HDTV). High yield devices can be obtained with the present invention.

Claims

1. A spatial light modulator, comprising:

a) an array of picture elements;

b) a plurality of memory cells arranged in rows controlling said picture elements;

c) memory cell addressing means for generating row address signals; and

d) a mapping circuit coupled between said addressing means and said memory cell rows for selectively determining which subset of said memory cell rows are addressed by said row address signals to control said picture elements, said mapping circuit having a separate logic cell associated with each said memory cell row, each said logic cell having two inputs receiving two of said row address signals and an output driving said associated memory cell row.

2. The spatial light modulator as specified in claim 1 wherein said logic cells conduct zero current between either of two said inputs and said output.

3. The spatial light modulator as specified in claim 1 wherein said mapping circuit further comprises a fused circuit programming said mapping circuit, said logic cells addressing said associated row of memory cells as a function of said fused circuit and one said row address signal at one of said two inputs.

4. The spatial light modulator as specified in claim 3 wherein said fused circuit comprises a network of interconnected fuses, one said fuse being associated with each said logic cell, whereby blowing one said fuse causes said mapping circuit to bypass a defective said memory cell and incorporate a known operable said memory cell.

5. The spatial light modulator as specified in claim 4 wherein one said fuse is associated with each row of said memory cells, whereby blowing one said fuse disables said associated row of memory cells.

6. The spatial light modulator as specified in claim 5 comprising primary said memory cells and spare said memory cells associated with said picture elements, with one said fuse being associated with each said spare memory cell, whereby blowing one said fuse connects said associated spare memory cell to said associated picture element.

7. The spatial light modulator as specified in claim 6 wherein one said spare memory cell is associated with a plurality of said primary memory cells.

8. The spatial light modulator as specified in claim 7 wherein one said primary memory cell is associated with a plurality of said picture elements.

9. The spatial light modulator as specified in claim 6 wherein said picture elements comprise a deflectable micromirror positioned over said memory cells, said micromirrors operable to deflect as a function of a content of an associated said memory cell.

10. The spatial light modulator as specified in claim 6 whereby said mapping circuit reconfigures mapping of said address signals from said addressing means to said memory cells when said spare memory cell is implemented.

11. A spatial light modulator, comprising;

a) an array of picture elements;

b) a plurality of primary memory cells associated with and controlling said picture elements;

c) at least one spare memory cell; and

d) memory cell formatting circuit means associated with said primary memory cells and said spare memory cells for selectively implementing one said spare memory cell in place of one said primary memory cell and functionally disabling said replaced primary memory cell, wherein said memory cell formatting circuit means comprises a network of fuses and a mapping circuit responsive to said network of fuses, said network of fuses comprising a series of fuses connected to ground on one end, and connected to a switch at the other end, said switch providing a potential to said series of fuses only when said spare memory cell is implemented, said series of fuses conducting substantially no current when said spare memory cells are not implemented.

12. The spatial light modulator as specified in claim 11 wherein said network of fuses conducts substantially no current when said spare memory cells are implemented.

13. The spatial light modulator as specified in claim 11 wherein each said spare memory cell is associated with a plurality of said primary memory cells.

14. The spatial light modulator as specified in claim 11 wherein one said fuse is associated with each said primary memory cell.

15. The spatial light modulator as specified in claim 11 wherein one said fuse is associated with each said spare memory cell.

16. The spatial light modulator as specified in claim 11 wherein said picture elements comprise a deflectable micromirror positioned over said primary memory cells and operable to deflect as a function of a content of an associated said primary memory cell.

17. The spatial light modulator as specified in claim 11 wherein said primary memory cells and said spare memory cells are arranged in an array with each said spare memory cell associated with and positioned proximate a group of adjacent said primary memory cells.

18. The spatial light modulator as specified in claim 17, wherein said network of fuses is positioned lateral of said array of memory cells.

19. The spatial light modulator as specified in claim 11, wherein said fuse network includes a logic circuit controlling which primary memory cells are utilized as a function of which said fuses are blown.

20. A memory cell, comprising:

a) a plurality of memory cells arranged in rows;

b) memory cell addressing means for generating row address signals; and

c) a mapping circuit coupled between said addressing means and said memory cell rows for selectively determining which subset of said memory cell rows are addressed by said row address signals, said mapping circuit having a separate logic cell associated with each said memory cell row, each said logic cell having two inputs receiving two of said row address signals and an output driving said associated memory cell row.

21. A memory cell array, comprising;

a) an array of primary memory cells arranged in rows;

b) at least one row of spare memory cells; and

c) memory cell formatting circuit means associated with said primary memory cells and said spare memory cells for selectively implementing one said spare memory cell row in place of one said primary memory cell row and functionally disabling said replaced primary memory cell row, wherein said memory cell formatting circuit means comprises a mapping circuit responsive to a network of fuses, said network of fuses comprising a series of fuses connected to ground, on one end, and connected to a switch at the other end, said switch providing a potential to said series of fuses only when said spare memory cell is implemented, said series of fuses conducting substantially no current when said spare memory cells are not implemented.