Spatial light modulator having single bit-line dual-latch memory cells
First Claim
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1. A spatial light modulator, comprising:
- an array of electrically addressable pixels, arranged in rows and columns;
a memory cell array, arranged in rows and columns, each memory cell being in data communication with at least one of said pixels, each said memory cell having a first latch in data communication with a second latch, said first latch transferring pixel data to said second latch in response to a transfer signal, said second latch providing an address signal representative of said pixel data to said at least one of said pixels with which said memory cell is in data communication;
a bit-line associated with each said column of said memory cell array, each said bit-line delivering said pixel data to the first latch of each said memory cell in its associated column of said memory cell array; and
a write word-line associated with each said row of said memory cell array, each said word-line delivering a write signal enabling its associated row of said memory cell array to be written with said pixel data.
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Abstract
A spatial light modulator (SLM) device (30) having a pixel array (31) and an associated memory cell array (36). Each memory cell (10a) receives pixel data from a single bit-line that carries pixel data down columns of the memory cell array (36). Each memory cell (10a) has two latches (21, 25). A first latch (21) receives data from the bit-line. A second latch (25) receives data transferred from the first latch (21) in response to a transfer signal, and is in electrical communication with at least one address electrode (14) of each pixel (10) of the pixel array (31).
40 Citations
19 Claims
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1. A spatial light modulator, comprising:
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an array of electrically addressable pixels, arranged in rows and columns; a memory cell array, arranged in rows and columns, each memory cell being in data communication with at least one of said pixels, each said memory cell having a first latch in data communication with a second latch, said first latch transferring pixel data to said second latch in response to a transfer signal, said second latch providing an address signal representative of said pixel data to said at least one of said pixels with which said memory cell is in data communication; a bit-line associated with each said column of said memory cell array, each said bit-line delivering said pixel data to the first latch of each said memory cell in its associated column of said memory cell array; and a write word-line associated with each said row of said memory cell array, each said word-line delivering a write signal enabling its associated row of said memory cell array to be written with said pixel data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A digital micro-mirror device comprising:
- an array of mirror elements, each mirror element being electrically addressable in response to an address signal applied at an address electrode;
a memory cell array, arranged in rows and columns, for storing pixel data representing the state of said address signal, each memory cell being in data communication with at least one of said mirror elements, wherein each said memory cell has a first latch and a second latch in data communication with said first latch, said first latch transferring said pixel data to said second latch in response to a transfer signal, said second latch providing said address signal to at least one said pixel; a single bit-line associated with each said column of said memory cell array, each said bit-line delivering pixel data to its associated column of said memory cell array; and a write word-line associated with each said row of said memory cell array, each said word-line delivering a write signal enabling its associated row of said memory cell array to be written with said pixel data. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
- an array of mirror elements, each mirror element being electrically addressable in response to an address signal applied at an address electrode;
Specification