Modulation, demodulation and antenna coupling circuits used in IC card reading/writing apparatus, and method of supplying power to the IC card
First Claim
1. A demodulation circuit having a carrier synchronizer and a bit synchronizer, and used in an IC card reading/writing apparatus, wherein said carrier synchronizer comprises:
- a carrier sync signal generation circuit for generating a carrier sync signal;
an exclusive logical sum circuit which receives a signal modulated by binary phase shift keying sent from an IC card and the carrier sync signal provided by said carrier sync signal generation circuit;
a sync gate counter which counts up or count down clock pulses of said reading/writing apparatus depending on the output signal of said exclusive logical sum circuit;
a majority discriminator which determines, while said sync gate counter performs a count operation during a half cycle of the carrier sync signal, the majority level of the signal modulated by binary phase shift keying thereby to detect as to whether the carrier sync signal and the BPSK-modulated signal are in common phase or opposite phase;
a former/latter halves comparator which compares the duration of a pulse of the signal modulated by binary phase shift keying between the former half and latter half of a half period of the carrier sync signal; and
a sync control circuit which controls said carrier sync signal generation circuit thereby to control the phase of the carrier sync signal in response to the detection as to whether the carrier sync signal is in lead-phase or lag-phase relative to the signal modulated by binary phase shift keying based on the detection result of said majority discriminator and the comparison result of said former/latter comparator.
2 Assignments
0 Petitions
Accused Products
Abstract
A modulator used in an IC card reader/writer includes a phase variation detector for detecting a varying point of the phase of a modulated signal, a signal processing circuit for modifying the modulated signal for a half period at the phase varying point to have a frequency and amplitude twice those of the modulated signal, a first Miller integrator for integrating the modified signal to produce a triangular wave signal, and a second Miller integrator for integrating the triangular wave signal to produce a sinusoidal wave signal having a continuous phase. A demodulator used in the reader/writer includes a sync control circuit which controls a carrier sync signal generation circuit thereby to control the phase of a carrier sync signal in response to the discrimination as to whether the carrier sync signal is in lead-phase or lag-phase relative to the signal modulated based on binary phase shift keying (BPSK). A control data signal and non-modulated carrier wave sent from the reader/writer to the IC card are converted into power for use by the IC card.
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Citations
2 Claims
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1. A demodulation circuit having a carrier synchronizer and a bit synchronizer, and used in an IC card reading/writing apparatus, wherein said carrier synchronizer comprises:
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a carrier sync signal generation circuit for generating a carrier sync signal; an exclusive logical sum circuit which receives a signal modulated by binary phase shift keying sent from an IC card and the carrier sync signal provided by said carrier sync signal generation circuit; a sync gate counter which counts up or count down clock pulses of said reading/writing apparatus depending on the output signal of said exclusive logical sum circuit; a majority discriminator which determines, while said sync gate counter performs a count operation during a half cycle of the carrier sync signal, the majority level of the signal modulated by binary phase shift keying thereby to detect as to whether the carrier sync signal and the BPSK-modulated signal are in common phase or opposite phase; a former/latter halves comparator which compares the duration of a pulse of the signal modulated by binary phase shift keying between the former half and latter half of a half period of the carrier sync signal; and a sync control circuit which controls said carrier sync signal generation circuit thereby to control the phase of the carrier sync signal in response to the detection as to whether the carrier sync signal is in lead-phase or lag-phase relative to the signal modulated by binary phase shift keying based on the detection result of said majority discriminator and the comparison result of said former/latter comparator. - View Dependent Claims (2)
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Specification