Symbol timing recovery based on complex sample magnitude

• US 5,671,257 A
• Filed: 06/06/1995
• Issued: 09/23/1997
• Est. Priority Date: 06/06/1995
• Status: Expired due to Term

• Current Assignee: Rousseau Investment Group LLC (Intellectual Ventures LLC)
• Original Assignee: SiCOM, Inc. (Renesas Electronics Corporation)
• Inventors: McCallister, Ronald D., Cochran, Bruce A.
• Primary Examiner(s): Bocure, Tesfaldet
• Application Number:
  US08/468,921
• Time in Patent Office: 840 Days
• Field of Search: 375/355, 375/354, 375/376, 375/371, 327/91, 327/299, 327/141, 328/72
• US Class Current: 375/355
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H04L 7/0054 Detection of the synchronisation error by features other than the received signal transition by means of signal transition H04L7/033
• CPC Class Codes: H04L 7/0083 taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
• CPC Class Codes: H04L 7/0334 Processing of samples having at least three levels, e.g. soft decisions

Abstract

A digital communication receiver (10) takes one complex sample (20) of a baseband analog signal (12) per symbol. A rectangular to polar converter (26) separates phase attributes of the complex samples from magnitude attributes. A phase processor (28) identifies clock adjustment opportunities which occur when relatively large phase changes take place between consecutive symbols. A magnitude processor (32) influences symbol timing only during clock adjustment opportunities. The magnitude processor (32) advances symbol timing in a phase locked loop when decreasing magnitude changes are detected during clock adjustment opportunities and retards symbol timing when increasing magnitude changes are detected during clock adjustment opportunities. An interpolator (66) may be used to estimate magnitude values between samples so that magnitude change is determined between sampled magnitude values and estimated magnitude values.

Claims

1. In a digital communication receiver, a method of recovering symbol timing from an analog signal configured as a stream of symbols, said method comprising the steps of:

generating a clock signal which defines symbol timing;

sampling said analog signal in response to said clock signal to generate less than two complex samples for each symbol;

separating magnitude attributes of said less than two complex samples for each symbol from phase attributes of said less than two complex samples for each symbol so that said magnitude attributes are substantially insensitive to phase changes; and

adjusting said symbol timing defined by said clock signal in response to at least a portion of said magnitude attributes.

5. A method of recovering symbol timing as claimed in claim 1 wherein said adjusting step comprises the step of estimating changes occurring in a complex magnitude characteristic of said analog signal over at least portions of symbols so that said symbol timing is adjusted in response to estimated magnitude characteristic change.

2. In a digital communication receiver, a method of recovering symbol timing from an analog signal configured as a stream of symbols, said method comprising the steps of:

generating a clock signal which defines symbol timing;

sampling said analog signal in response to said clock signal to generate a complex sample for each symbol;

separating magnitude attributes of said complex samples from phase attributes of said complex samples so that said magnitude attributes are substantially insensitive to phase changes;

identifying clock adjustment opportunities in response to said phase attributes of said complex samples; and

enabling at least a portion of said magnitude attributes which are approximately coincident with said clock adjustment opportunities to adjust said symbol timing; and

adjusting said symbol timing defined by said clock signal in response to said portion of said magnitude attributes.

3. A method of recovering symbol timing as claimed in claim 2 wherein:

said identifying step comprises the step of determining changes occurring in said phase attributes; and

said clock adjustment opportunities are identified in response to said changes in said phase attributes.

4. A method of recovering symbol timing as claimed in claim 3 wherein said identifying step further comprises the steps of:

defining occurrences of relatively larger phase change as being clock adjustment opportunities; and

defining occurrences of relatively smaller phase change as not being clock adjustment opportunities.

6. In a digital communication receiver, a method of recovering symbol timing from an analog signal configured as a stream of symbols, said method comprising the steps of:

generating a clock signal which defines symbol timing;

sampling said analog signal in response to said clock signal to generate a complex sample for each symbol;

identifying clock adjustment opportunities in response to phase relationships exhibited by said complex samples; and

adjusting said symbol timing defined by said clock signal in response to magnitude relationships exhibited by said complex samples at approximately said identified clock adjustment opportunities.

7. A method of recovering symbol timing as claimed in claim 6 additionally comprising the step of generating a magnitude value and a phase value for each complex sample.

8. A method of recovering symbol timing as claimed in claim 6 wherein said sampling step is configured to sample said analog signal at a rate of less than two complex samples per symbol.

9. A method of recovering symbol timing as claimed in claim 6 additionally comprising the step of detecting data conveyed by said analog signal, said detecting data step being responsive to said complex samples.

10. A method of recovering symbol timing as claimed in claim 6 wherein:

said identifying step comprises the step of determining changes occurring in said phase relationships; and

said clock adjustment opportunities are identified in response to said changes in said phase relationships.

11. A method of recovering symbol timing as claimed in claim 10 wherein said identifying step further comprises the steps of:

defining occurrences of relatively larger phase change as being clock adjustment opportunities; and

defining occurrences of relatively smaller phase change as not being clock adjustment opportunities.

12. A method of recovering symbol timing as claimed in claim 10 wherein said identifying step further comprises the steps of:

establishing a threshold which is greater than π

/4;

defining occurrences of phase change between consecutive symbols which are greater than said threshold as being clock adjustment opportunities; and

defining occurrences of phase change between consecutive symbols which are less than said threshold as not being clock adjustment opportunities.

13. A method of recovering symbol timing as claimed in claim 6 wherein said adjusting step comprises the step of detecting changes occurring in said magnitude relationships over at least portions of symbols which are substantially coincident with said clock adjustment opportunities.

14. A method of recovering symbol timing as claimed in claim 13 wherein said adjusting step further comprises the step of advancing said symbol timing when an increasing magnitude relationship is detected in said detecting step.

15. A method of recovering symbol timing as claimed in claim 13 wherein said adjusting step further comprises the step of delaying said symbol timing when a decreasing magnitude relationship is detected in said detecting step.

16. A method of recovering symbol timing as claimed in claim 6 wherein:

said sampling step samples said analog signal at sampling instants so that said complex samples and said magnitude relationships thereof correspond to said analog signal at said sampling instants;

said adjusting step comprises the step of interpolating said magnitude relationships exhibited by said complex samples at said sampling instants to estimate magnitude relationships occurring between said sampling instants; and

said adjusting step further comprises the step of determining changes between said magnitude relationships and said estimated magnitude relationships.

17. A symbol synchronizer for recovering symbol timing in a digital communication receiver which receives an analog signal configured as a stream of symbols, said symbol synchronizer comprising:

an oscillator for generating a clock signal which defines symbol timing;

an analog-to-digital converter, coupled to said oscillator, for sampling said analog signal to generate a complex sample for each symbol;

a phase processor, coupled to said converter, for identifying clock adjustment opportunities in response to phase relationships exhibited by said complex samples; and

a magnitude processor, coupled to said converter, said phase processor, and said oscillator, for adjusting said symbol timing defined by said clock signal in response to magnitude relationships exhibited by said complex samples at approximately said identified clock adjustment opportunities.

18. A symbol synchronizer as claimed in claim 17 additionally comprising a rectangular-to-polar converter having an input coupled to said analog-to-digital converter, having a phase output coupled to said phase processor, and having a magnitude output coupled to said magnitude processor.

19. A symbol synchronizer as claimed in claim 17 wherein said oscillator and said converter are configured to sample said analog signal at a rate of less than two complex samples per symbol.

20. A symbol synchronizer as claimed in claim 17 wherein said phase processor comprises:

a delay element, coupled to said converter, for generating at a current instant a phase relationship exhibited by said complex sample at a past instant; and

a subtractor, coupled to said converter and said delay element, for determining changes occurring in said phase relationships between said current and past instants.

21. A symbol synchronizer as claimed in claim 20 additionally comprising a comparison element coupled to said subtractor, said comparison element being configured so that occurrences of relatively larger phase change are defined as being clock adjustment opportunities and so that occurrences of relatively smaller phase change are defined as not being clock adjustment opportunities.

22. A symbol synchronizer as claimed in claim 17 wherein said magnitude processor comprises:

a delay element, coupled to said converter, for generating at a current instant a magnitude relationship exhibited by said complex sample at a past instant, said current and past instants being approximately coincident with one of said clock adjustment opportunities; and

a subtractor, coupled to said converter and said delay element, for determining changes occurring in said magnitude relationships between said current and past instants.

23. A symbol synchronizer as claimed in claim 22 wherein said magnitude processor is configured in cooperation with said oscillator so that symbol timing is advanced when said subtractor detects an increasing magnitude relationship during one of said clock adjustment opportunities and so that said symbol timing is delayed when said subtractor detects a decreasing magnitude relationship during one of said clock adjustment opportunities.

24. A symbol synchronizer as claimed in claim 22 wherein:

said oscillator and said converter are configured to sample said analog signal at sampling instants so that said complex samples and said magnitude relationships thereof correspond to said analog signal at said sampling instants; and

said delay element comprises an interpolator configured to estimate magnitude relationships occurring between said sampling instants.