PCMCIA interface card coupling input devices such as barcode scanning engines to personal digital assistants and palmtop computers

• US 5,671,374 A
• Filed: 04/25/1995
• Issued: 09/23/1997
• Est. Priority Date: 04/29/1994
• Status: Expired due to Term

• Current Assignee: Datalogic Mobile Incorporated (Datalogic S.p.A.), Datalogic Scanning Incorporated (Datalogic S.p.A.), TPS Electronics
• Original Assignee: TPS Electronics
• Inventors: Fish, Ronald C., Postman, Joel R., Miller, George B.
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US08/428,692
• Time in Patent Office: 882 Days
• Field of Search: 395/309, 395/310, 395/412, 395/892, 395/285, 395/286, 395/882, 395/883, 395/884, 395/282, 395/283, 235/492, 235/472
• US Class Current: 710/305
• CPC Class Codes: G01D 2213/10 Drivers for gauges
• CPC Class Codes: G06F 1/1626 with a single-body enclosure integrating a flat display, e.g. Personal Digital Assistants [PDAs]
• CPC Class Codes: G06F 1/1632 External expansion units, e.g. docking stations
• CPC Class Codes: G06F 3/00 Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
• CPC Class Codes: G06F 3/002 Specific input/output arrangements not covered by G06F3/01 - G06F3/16 other optical apparatus G02B27/00
• CPC Class Codes: G06F 3/023 Arrangements for converting discrete items of information into a coded form, e.g. arrangements for interpreting keyboard generated codes as alphanumeric codes, operand codes or instruction codes
• CPC Class Codes: G06F 3/038 Control and interface arrangements therefor, e.g. drivers or device-embedded control circuitry
• CPC Class Codes: G06F 3/0383 Signal control means within the pointing device

Abstract

A variety of PC card interfaces to interface from many different types of input devices to Personal Digital Assistants or palmtop computers through PCMCIA slots. The disclosed interfaces can receive data in undecoded format from laser based, wand based or CCD based barcode scanning engines, decode the data to alphanumeric characters and pass the decoded data to the PDA via the PCMCIA 68 pin bus. Other PC card based interfaces are also disclosed which can accept input data in the form of ASCII or EBCDIC characters from virtually any type of input device which a standard serial or parallel output or custom output bus and input that data to the PDA through the PCMCIA bus. Some embodiments use programmed general purpose microprocessors to decode undecoded barcode scan data on the PC card. Other embodiments use custom-programmed, commercially available barcode decoding chips to decode incoming undecoded barcode scan data. Some embodiments of PC card interfaces sample undecoded barcode scan signals and pass the samples to the host through the PCMCIA bus for decoding by a suitably programmed host computer.

Claims

1. An interface circuit, said interface circuit for coupling an input device that can generate electrical signals encoding alphanumeric characters to a host computer with a PCMCIA slot housing a PCMCIA bus connector which is coupled to a system bus of said host computer via a PC card having a PCMCIA bus connector which mates with the PCMCIA bus connector of said host computer, comprising:

on a PC card;

an input port for receiving said electrical signals from said input device;

a PCMCIA bus connector;

a decoder circuit coupled to said input port so as to receive said electrical signals, said decoder circuit for decoding said electrical signals to generate one or more alphanumeric characters and for notifying said host computer when at least one successful decoding operation has occurred and at least one alphanumeric character resulting from decoding operations is available on said PC card for access by said host computer; and

an interface circuit having hardware and software components on both said PC card and within said host computer, and coupled to said decoder circuit on said PC card and to said PCMCIA bus connector on said PC card and coupled to said PCMCIA connector of said host computer, said interface circuit for facilitating coupling said decoder circuit to said host computer via said PCMCIA bus connectors such that said notification of a successful decoding operation can be passed to said host computer via said PCMCIA bus connectors and for controlling operations of said host computer to retrieve said one or more decoded alphanumeric characters from said PC card via said PCMCIA bus connectors in response to receiving notification of a successful decoding operation.

2. The apparatus of claim 1 wherein said input device is physically mounted on said PC card.

3. The apparatus of claim 2 further comprising nonvolatile memory physically mounted on said PC card and coupled to said host computer through said PCMCIA bus connector for access by said host computer or said decoder circuit.

4. The apparatus of claim 3 wherein said decoder circuit is of the class of commercially available barcode decoding integrated circuits which is defined by the integrated circuit manufactured by Hewlett Packard and marketed under the model designation HP 2312 as of the time of filing of this patent application.

5. The apparatus of claim 4 wherein said interface circuit includes an interface adapter circuit of the class of commercially available PCMCIA interface adapter integrated circuits typified by the integrated circuit manufactured by Zilog under the model designation Z86017 as of the time of filing of this patent application.

6. The apparatus of claim 2 wherein said interface circuit includes an interface adapter circuit of the class of commercially available PCMCIA interface adapter integrated circuits typified by the integrated circuit manufactured by Zilog under the model designation Z86017 as of the time of filing of this patent application, and wherein said input device is a barcode scan engine which is physically mounted on said PC card.

7. The apparatus of claim 1 wherein said PC card further comprises nonvolatile memory coupled for access by said host computer through said PCMCIA bus connector and wherein said interface circuit includes means for providing access to said nonvolatile memory on said PC card by said host computer either before or after data transfers between said host computer and said decoder on said PC card without rebooting said host computer.

8. An interface circuit, said interface circuit for coupling between an input device that can generate electrical signals encoding alphanumeric characters and a host computer with a PCMCIA slot housing a PCMCIA bus connector coupled to a system bus of said host computer, comprising:

on a PC card having a form factor defined by a PCMCIA specification as it existed as of the time of this patent application;

nonvolatile memory for access by said host computer;

an input interface circuit for receiving electrical signals from said input device in whatever form they are sent and converting them to a useable form;

a PCMCIA bus connector;

a decoder circuit coupled to said input interface circuit so as to receive said electrical signals after conversion by said input interlace circuit to a form useable by said decoder circuit, said decoder circuit for decoding said electrical signals to generate one or more alphanumeric characters encoded in said electrical signals and for generating data indicative of a successful decoding operation when at least one successful decoding operation has occurred and at least one alphanumeric character resulting from decoding operations is available on said PC card for access by said host computer; and

an interface circuit having hardware and software components on both said PC card and within said host computer, and coupled to said decoder circuit and to said PCMCIA bus connector on said PC card and to said PCMCIA bus connector of said host computer, for facilitating coupling of said decoder circuit to said host computer via said PCMCIA bus connectors on said host computer and said PC card such that said notification of a successful decoding operation can be implemented by signals passing between said host computer and said PC card via said PCMCIA bus connectors and so that said host computer can retrieve said one or more decoded alphanumeric characters from said PC card via said PCMCIA bus connectors and wherein said interface circuit includes means for providing access to said nonvolatile memory on said PC card by said host computer either before or after data transfers between said host computer and said decoder circuit on said PC card without rebooting said host computer.

9. The apparatus of claim 8 wherein said decoder circuit is of the class of commercially available barcode decoding integrated circuits of which is typical the integrated circuit manufactured by Hewlett Packard and marketed under the model designation HP 2312 as of the time of filing of this patent application.

10. The apparatus of claim 8 wherein said PC card has an I/O mode and a memory mode, and wherein said PCMCIA bus connector has data bus pins comprising high byte data pins and low byte data pins, address pins and a plurality of pins carrying a first plurality of control signals in I/O mode and a second plurality of signals in memory mode, at least one of said control signals being an interrupt, and wherein said nonvolatile memory is comprised of a high byte flash memory for storing the high byte of every stored word and a low byte flash memory for storing the low byte of information of every stored word, and wherein each of said high byte and low byte flash memories has an address port coupled to said address pins of said PCMCIA bus connector and has a data port, said interface circuit comprising:

a bidirectional high byte steering buffer having a first data port coupled to the high byte data pins of said PCMCIA data bus, and having a second data port coupled to said data port of said high byte flash memory, and having a chip select input;

a bidirectional low byte steering buffer having a first data port coupled to the low byte data pins of said PCMCIA data bus, and having a second data port coupled to said data port of said high byte flash memory, and having a chip select input;

a card information nonvolatile memory for storing data defining a Card Information Structure, and having a data port coupled to said low byte data pins of said PCMCIA bus, and having a chip select input;

a configuration option register for storing data sent by the host computer controlling whether said PC card is in memory mode or I/O mode, and having a data port coupled to said low byte data pins of said PCMCIA bus, and having a chip select input;

a card status register for storing data sent by the host computer which controls whether interrupts can be generated and controlling whether the PC card sends an audio feedback signal generated by said decoder to said host computer, and having a data pod coupled to said low byte data pins of said PCMCIA bus, and having a chip select input;

a pin replace register for storing the states of predetermined control signals on said PCMCIA bus in memory mode which are carried on shared pins of the PCMCIA bus that are used for other control signals in I/O mode, and having a data port coupled to said low byte data pins of said PCMCIA bus, and having a chip select input;

a control register for storing pacing signals involved in a handshaking protocol for data transfers between said PC card and said host computer via said PCMCIA bus, and having a data port coupled to said low byte data pins of said PCMCIA bus, and coupled to said decoder such that said decoder can read said pacing signals, and having a chip select input;

a status register coupled to said decoder for storing predetermined pacing signals generated by said decoder and involved in said handshaking protocol for data transfers between said PC card and said host computer via said PCMCIA bus, and having a data port coupled to said low byte data pins of said PCMCIA bus, and having a chip select input;

a command register coupled to said decoder by a multiplexed data/address bus, and having a data port coupled to said low byte data pins of said PCMCIA bus, and having a chip select input, for storing ASCII character strings sent by said host computer to said PC card to control operations by said decoder;

a data register coupled to said decoder by said multiplexed data/address bus, and having a data port coupled to said low byte data pins of said PCMCIA bus, and having a chip select input, for storing one or more alphanumeric characters decoded by said decoder temporarily until said one or more alphanumeric characters are sent to said host computer;

a static random access memory having an address port having a plurality of pins some of which are coupled to address output pins of said decoder, and having a data port coupled to said decoder via said multiplexed data/address bus;

an address latch coupled to said decoder by said multiplexed data/address bus, for storing address data sent by said decoder, and having an address output port coupled to the address pins of said address port of said static random access memory which are not coupled to said decoder;

a control and interrupt logic circuit coupled to said interrupt control signal pin of said PCMCIA bus connector on said PC card, and coupled to said chip select inputs of said card info nonvolatile memory, said high byte flash memory, said low byte flash memory, said configuration option register, said card status register, said pin replace register, said control register, said status register, said command register and said data register, and coupled to receive predetermined control and address signals from said PCMCIA bus pins on the PCMCIA bus connector and to receive predetermined control signals generated on said PC card, for activating predetermined chip select signals based upon predetermined combinations of logic states of said control and address signals, and for generating data indicative of a successful decoding operation when at least one successful decoding operation has occurred by activating said interrupt signal to said host computer based upon predetermined combinations of logic states of said control and address signals.

11. The apparatus of claim 9 further comprising a headphone interface circuit coupled to said decoder circuit for driving headphones using a digital audio signal generated by said decoder circuit.

12. The apparatus of claim 9 further comprising a motion sensor coupled to said interface circuit for generating a signal which indicates when motion is sensed in front of said motion sensor, and wherein said interface circuit includes circuitry for coupling said motion sensor circuit to a barcode client application controlling execution by said host computer such that said barcode client application can send a signal to said decoder circuit to cause said input device to start operating and to cause said decoder to start decoding signals from said input device.

13. The apparatus of claim 9 further comprising a conventional trigger switch coupled to said interface circuit for generating a signal which indicates when operation by said input device is desired, and wherein said interface circuit includes circuitry for coupling said trigger switch to a barcode client application controlling execution by said host computer such that said barcode client application can send a signal to said decoder circuit to cause said input device to start operating and to cause said decoder to start decoding signals from said input device.

14. The apparatus of claim 9 further comprising a motion sensor coupled to said interface circuit for generating a signal which indicates when motion is sensed in front of said motion sensor, and wherein said interface circuit includes circuitry for coupling said signal output by said motion sensor circuit to said decoder circuit to cause said decoder circuit to generate a signal to cause said input device to start operating.

15. The apparatus of claim 9 further comprising a conventional hand operated trigger switch coupled to said interface circuit for generating a signal which indicates when operation by said input device is desired, and wherein said interface circuit includes circuitry for coupling said signal output by said hand operated trigger switch to said decoder circuit to cause said decoder circuit to generate a signal to cause said input device to start operating.

16. An interface circuit, said interface circuit for coupling an input device that can generate electrical signals representing alphanumeric characters encoded in spatial patterns of contrasting areas of an image or representing some other type of code which encodes alphanumeric information to a host computer with a PCMCIA slot housing a PCMCIA bus connector, comprising:

on a PC card having a form factor defined by PCMCIA standards as they existed at the time this patent application was filed;

an input port for receiving electrical signals from said input device;

a PCMCIA bus connector;

decoder means coupled to said input port so as to receive said electrical signals, for decoding said electrical signals to generate one or more alphanumeric characters encoded in said electrical signals and for notifying said host computer when at least one successful decoding operation has occurred and at least one alphanumeric character resulting from decoding operations is available on said PC card for access by said host computer; and

PCMCIA interface means coupled to said decoder means and to said PCMCIA bus connector on said PC card, for coupling said decoder means to said host computer via said PCMCIA bus connectors such that said notification of a successful decoding operation can be passed to said host computer via said PCMCIA bus connectors and so that said host computer can retrieve said one or more decoded alphanumeric characters from said PC card via said PCMCIA bus connectors.

17. The apparatus of claim 16 wherein said input device is a barcode scan engine and wherein said barcode scan engine is physically attached to said PC card and coupled to supply to said input port said electrical signals encoding said alphanumeric characters therein.

18. The apparatus of claim 17 further comprising nonvolatile memory on said PC card for access by said host computer, and wherein said PC card can operate in I/O mode or memory mode and wherein said PCMCIA interface means includes means for providing access by said host computer both to said alphanumeric characters generated by said decoder means and data stored in said nonvolatile memory, access to said alphanumeric characters generated by said decoder being via I/O mode transactions and access to data stored in said nonvolatile memory being via memory mode transactions.

19. The apparatus of claim 16 wherein said PC card has a memory mapping which includes an attribute space and an I/O space, and further includes one or more registers for storing control data generated by said host computer and transmitted to said PC card and control data generated by said PC card and for storing alphanumeric characters generated by said decoder means, said one or more registers mapped into the attribute space and I/O space of said PC card'"'"'s memory mapping, and wherein said PCMCIA interface means includes card services means for controlling operations of said host computer to assign an interrupt number and a base address in said I/O space mapping of said host computer to said PC card each time said PC card is inserted into a PCMCIA slot on said host computer and further includes PC Card driver means controlling operations by said host computer to determine, each time said PC card is inserted into a PCMCIA slot on said host computer, said interrupt number assigned to the PC card by said card services means and said assigned base address in said I/O space mapping of said host computer where one or more of said registers on said PC card can be found each time the PC card is inserted into the PCMCIA slot of the host computer, and wherein said PCMCIA interface means includes means for generating an interrupt signal to said host computer when at least one successful decoding operation has occurred and at least one alphanumeric character is stored in a register on said PC Card and is waiting to be read by said host computer, and wherein said PCMCIA interface means includes means controlling execution by said host computer to detect said interrupt signal and vector to an interrupt service routine pointed to by said interrupt number assigned to said PC card and to use computer program instructions of said interrupt service routine to control operations of said host computer to retrieve said at least one alphanumeric character stored on said PC card.

20. An interface circuit, said interface circuit for coupling between a barcode scan engine that can generate electrical signals encoding alphanumeric encoded within spatial patterns of contrasting areas of a barcode and a host computer with a PCMCIA slot housing a PCMCIA bus connector, comprising:

on a PC card being in the form factor defined by any PCMCIA standard as the PCMCIA standards existed at the time of filing of this patent application;

a nonvolatile memory on said PC card for access by said host computer;

a barcode scan engine physically attached to said PC card and coupled to supply electrical signals encoding said alphanumeric characters encoded within contrasting patterns of a barcode scanned by said barcode scan engine;

an input port for receiving electrical signals from said barcode scan engine resulting from scanning of a barcode;

a PCMCIA bus connector;

decoder coupled to said input port so as to receive said electrical signals, for decoding said electrical signals to generate one or more alphanumeric characters encoded in the spatial patterns of said barcode and for notifying said host computer when at least one successful decoding operation has occurred and at least one alphanumeric character resulting from decoding operations is available on said PC card for access by said host computer; and

a PCMCIA interface coupled to said decoder circuit and to said PCMCIA bus connectors on said PC card and on said host computer, for coupling said decoder circuit to said host computer via said PCMCIA bus connectors such that said notification of a successful decoding operation can be passed to said host computer via said PCMCIA bus connectors and for controlling said host computer so that said host computer can retrieve said one or more decoded alphanumeric characters from said PC card via said PCMCIA bus connectors, and wherein said PCMCIA interface means includes means for controlling said host computer so as to be able to access both to said alphanumeric characters generated by said decoder and data stored in said nonvolatile memory without rebooting said host computer.

21. The apparatus of claim 20 wherein said PC card includes one or more registers for storing control data generated by said host computer and transmitted to said PC card and control data generated by said PC card and for storing alphanumeric characters generated by said decoder means, said one or more registers mapped into the attribute space and I/O space of said PC card'"'"'s memory mapping, and wherein said PCMCIA interface means includes card services means for controlling operations of said host computer to assign an interrupt number and a base address in said I/O space mapping of said host computer to said PC card each time said PC card is inserted into a PCMCIA slot on said host computer and further includes PC Card driver means controlling operations by said host computer to determine, each time said PC card is inserted into a PCMCIA slot on said host computer, said interrupt number assigned to the PC card by said card services means and said assigned base address in said I/O space mapping of said host computer where one or more of said registers on said PC card can be found each time the PC card is inserted into the PCMCIA slot of the host computer, and wherein said PCMCIA interface circuit includes means for generating an interrupt signal to said host computer when at least one successful decoding operation has occurred and at least one alphanumeric character is stored in a register on said PC card and is waiting to be read by said host computer, and wherein said PCMCIA interface means includes means controlling execution by said host computer to detect said interrupt signal and vector to an interrupt service routine pointed to by said interrupt number assigned to said PC card and to use computer program instructions of said interrupt service routine to control operations of said host computer to retrieve said at least one alphanumeric character stored on said PC card.

22. An interface circuit, said interface circuit for coupling between an input device that can generate electrical signals encoding alphanumeric characters to a host computer having a PCMCIA slot housing a PCMCIA bus connector via a PC card, comprising:

an input port for receiving electrical signals from said input device that can generate electrical signals encoding said alphanumeric characters said electrical signals having a varying amplitude;

a PCMCIA bus connector for coupling to said PCMCIA bus connector of said host computer;

a PCMCIA interface adapter circuit coupled to receive said electrical signal from said input port, for converting said electrical signals into a plurality of digital sample values representing the amplitude of said electrical signals at various sample times and for coupling said sample values to said host computer through said PCMCIA bus connectors, said digital sample values for decoding into alphanumeric characters by said host computer.

23. The apparatus of claim 22 further comprising auxiliary nonvolatile memory on said PC card and wherein said interface circuit further comprises driver means controlling execution by said host computer so as to provide access by said host computer to said auxiliary nonvolatile memory on said PC card so that said host computer can read data or write data thereto via said PCMCIA bus connectors without preempting the data path through said PCMCIA bus connectors for said sample data such said PCMCIA bus connectors can still be used to transfer said sample data before and after accesses to said auxiliary nonvolatile memory without rebooting said host computer.

24. The apparatus of claim 22 further comprising decode means within said host computer for controlling said host computer to convert said digital samples of said electrical signal from said input device into the alphanumeric characters.

25. The apparatus of claim 23 further comprising decode means within said host computer for controlling said host computer to convert said digital samples into alphanumeric characters.