Method and apparatus for performing write operations in multi-level cell storage device

• US 5,671,388 A
• Filed: 05/03/1995
• Issued: 09/23/1997
• Est. Priority Date: 05/03/1995
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Hasbun, Robert N.
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): BRAGDON, REGINALD GLENWOOD
• Application Number:
  US08/433,614
• Time in Patent Office: 874 Days
• Field of Search: 395/430, 395/494, 395/492, 365/168, 365/185.03
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 2211/5642 Multilevel memory with buffers, latches, registers at input or output
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

Abstract

A memory contains a plurality of memory cells that are capable of storing one or more bits of data in each memory cell. The memory stores, in response to a write operation, data corresponding to the write operation in a first set of the memory cells such that each cell of the first set of the memory cells stores a single bit. Thereafter, data from the first set of memory cells are transferred to a second set of the memory cells such that each cell of the second set of the memory cells stores more than a single bit of data. The write operation to the first set of cells is executed in a foreground operation, and in a subsequent background operation, data from the first set of memory cells are transferred to the second set of memory cells. The memory cells are non-volatile flash electrically erasable programmable read only memory (EEPROM) cells, and therefore require erasure before programming. Typically, memory cells are reclaimed in a background operation. However, if not enough memory cells are available for a write operation, then a set of memory cells are reclaimed in a foreground operation, and more than one bit of the data are stored in the reclaimed memory cells.

Claims

1. A method for storing data in a memory comprising a plurality of cells capable of storing more than a single bit of data per cell, comprising the steps of:

storing data in a first set of said memory cells in accordance with a write operation to said memory,, wherein each cell of said first set of said memory cells stores a single bit of said data; and

storing said data from said first set of said memory cells in a second set of said memory cells, wherein each cell of said second set of said memory cells stores more than one bit of said data.

2. The method as set forth in claim 1, wherein:

the step of storing data in said first set of said memory cells comprises the step of storing said data in said first set of said memory cells in a foreground operation; and

the step of storing data in said second set of said memory cells comprises the step of storing said data in said second set of said memory cells in a background operation such that said background operation is executed when no accesses to said memory occurs.

3. The method as set forth in claim 1, further comprising the steps of:

determining whether said memory comprises available memory cells for use as said first set of said memory cells to store said data corresponding to said write operation;

reclaiming, as a foreground operation, a third set of memory cells in said memory prior to storing said data if said memory does not comprise enough available memory cells to store said data; and

storing, as a foreground operation, said data corresponding to said write operation in said third set of memory cells such that each cell of said third set of said memory cells stores more than a single bit of said data.

4. The method as set forth in claim 1, further comprising the steps of:

determining which memory cells are suitable to reclaim for re-use in a background operation; and

reclaiming, as a background operation, memory cells in said memory for re-use.

5. The method as set forth in claim 1, wherein the steps of storing data in said first and second sets of memory comprises the step of storing file data including control information and data.

6. The method as set forth in claim 5, wherein the step of storing file data comprises the step of storing an error correction code (ECC) with said file data.

7. The method as set forth in claim 1, wherein each set of said memory cells comprises blocks for storing a plurality of sectors, said memory cells in each block being erasable simultaneously.

8. The method as set forth in claim 1, wherein said memory cells comprise flash electrically erasable programmable read only memory (EEPROM) cells.

9. The method as set forth in claim 1, wherein the step of storing in a second set of said memory cells said data such that each cell of said second set of said memory cells stores more than a single bit of said data comprises the step of storing two bits of data in each of said second set of said memory cells.

10. A circuit for storing data comprising:

a plurality of memory cells capable of storing more than one bit per cell; and

a write circuit, wherein the write circuit stores data in a first set of said memory cells in accordance with a write operation, wherein each cell of said first set of said memory cells stores one bit of said data, wherein the write circuit subsequently stores said data from said first set of said memory cells in a second set of said memory cells, wherein each cell of said second set of said memory cells stores more than one bit of said data.

11. The circuit as set forth in claim 10, wherein said write circuit comprises:

a foreground mode of operation for storing data in said first set of said memory cells; and

a background mode of operation for storing said data in said second set of said memory cells such that said background operation is executed when no accesses to said memory occurs.

12. The circuit as set forth in claim 10, further comprising:

a controller circuit for determining whether said memory comprises available memory cells for use as said first set of said memory cells to store said data corresponding to said write operation, for reclaiming, as a foreground operation, a third set of memory cells in said memory prior to storing said data if said memory does not comprise enough available memory cells to store said data; and

said write circuit for storing, as a foreground operation, said data corresponding to said write operation in said third set of memory cells such that each cell of said third set of said memory cells stores more than a single bit of said data.

13. The circuit as set forth in claim 10, further comprising a controller circuit for determining which memory cells are suitable to reclaim for re-use in a background operation, and for reclaiming, as a background operation, memory cells in said memory for re-use.

14. The drcuit as set forth in claim 10, wherein said data comprises file data including control information and data.

15. The circuit as set forth in claim 14, wherein the step of storing file data comprises the step of storing an error correction code (ECC) with said data file.

16. The circuit as set forth in claim 10, wherein each set of said memory cells comprise blocks for storing a plurality of sectors, said memory cells in each block being erasable simultaneously.

17. The circuit as set forth in claim 10, wherein said memory cells comprise flash electrically erasable programmable read only memory (EEPROM) cells.

18. The circuit as set forth in claim 10, wherein said write circuit stores two bits of data in each of said second set of said memory cells.

19. A computer system, comprising:

a central processing unit (CPU);

memory coupled to said CPU; and

a solid state disk drive coupled to said CPU, said solid state disk drive comprising;

a plurality of memory cells capable of storing more than one bit per cell; and

a write circuit, wherein the write circuit stores data in a first set of said memory cells in accordance with a write operation, wherein each cell of said first set of said memory cells stores one bit of said data, wherein the write circuit subsequently stores said data from said first set of said memory cells in a second set of said memory cells, wherein each cell of said second set of said memory cells stores more than one bit of said data.

20. The computer system as set forth in claim 19, wherein said write circuit comprises:

a foreground mode of operation for storing data in said first set of said memory cells; and

a background mode of operation for storing said data in said second set of said memory cells such that said background operation is executed when no accesses to said memory occurs.