Microprocessor controlled apparatus

• US 5,671,434 A
• Filed: 06/07/1995
• Issued: 09/23/1997
• Est. Priority Date: 03/24/1992
• Status: Expired due to Fees

• Current Assignee: Nokia Mobile Phones UK Limited (Nokia Corporation)
• Original Assignee: Nokia Mobile Phones UK Limited (Nokia Corporation)
• Inventors: Menadue, Andrew, Withycombe, Ian
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): DARBE, VALERIE A
• Application Number:
  US08/478,551
• Time in Patent Office: 839 Days
• Field of Search: 395/800, 364/DIG. 1, 364/DIG. 2, 364/239, 364/240, 364/241.9, 364/240.1, 364/239.9, 364/240.3
• US Class Current: 712/38
• CPC Class Codes: G06F 13/4221 being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus

Abstract

A microprocessor controlled apparatus includes a microprocessor (2) with e.g. eight address lines (A,₀,A₁ . . . A₇) on which signals may be applied by the microprocessor for selectively addressing a peripheral device coupled thereto, and a data device such as a LCD module (1) having data lines to which data signals may be applied for transfer into the data device. Four of the data lines (D₀,D₁,D₂,D₃) are coupled to a sub-set of the microprocessor address lines (A₂,A₃,A₄,A₅) excluding the two address lines (A₀,A₁) associated with the least significant bits. The signals on the sub-set of address lines are thus applied as data signals to the data device. When data is to be transmitted to the data device the microprocessor (2) is caused to execute a sub-routine comprising instructions having addresses such that the signal appearing on the sub-set of address lines remains substantially stable over an extended period of time allowing data to be clocked into the device even when the write timing of the microprocessor is too fast for the device to accept data directly from the data output lines of the microprocessor.

Claims

1. A microprocessor controlled apparatus for providing signals to a device comprising:

a microprocessor having a plurality of dedicated address lines to which only address signals are applied during an instruction cycle, the microprocessor comprising means for maintaining all of the address signals on a sub-set of the address lines substantially constant between consecutive microprocessor instruction cycles; and

a device for receiving signals on a plurality of data lines, the data lines being coupled to the sub-set of the microprocessor address lines for receiving data on the data lines from the sub-set of address lines during a device write operation that extends over a plurality of microprocessor instruction cycles.

2. A microprocessor controlled apparatus as claimed in claim 1, wherein the microprocessor is adapted to maintain a substantially stable signal on each of the sub-set of address lines while the signal on other of the address lines is changed.

3. A microprocessor controlled apparatus as claimed in claim 2, wherein the microprocessor is conditioned to execute a sub-routine comprising instructions having addresses such that the signal appearing on the sub-set of address lines remains substantially stable during the execution of said sub-routine.

4. A microprocessor controlled apparatus as claimed in claim 3, wherein the sub-routine comprises at least one "no operation" instruction.

5. A microprocessor controlled apparatus as claimed in claim 3, wherein the sub-routine comprises m "no operation" instructions.

6. A microprocessor controlled apparatus as claimed in claim 1, wherein the sub-set of address lines excludes the address lines (A₀, . . . A_x) associated with the x least significant bits, where x is the number of digits in the binary representation of m+1, and m+1 is the number of data lines of the data device which are coupled to the sub-set of microprocessor address lines.

7. A microprocessor controlled apparatus as claimed in claim 6, wherein the sub-set of address lines excludes the address lines (A₀,A₁) associated with the two least significant bit positions.

8. A microprocessor controlled apparatus as claimed in claim 7, wherein the data device has four data lines (D₀,D₁,D₂,D₃) coupled respectively to the address lines (A₂,A₃,A₄,A₅) associated with the third to the sixth least significant bit positions.

9. A microprocessor controlled apparatus as claimed in claim 8, wherein the data device is an 8-bit device and data is applied to the four data lines sequentially in two 4-bit segments.

10. A microprocessor controlled apparatus as claimed in claim 1, wherein the data device includes a write line to which a write signal is applied from the microprocessor during the time the signals on the sub-set of address lines are held substantially stable whereby data is transferred to the data device from the data lines.

11. A microprocessor controlled apparatus as claimed in claim 1, wherein the maximum speed at which the data device can accept data is less than the microprocessor outputs data.

12. A microprocessor controlled apparatus as claimed in claim 1, wherein the data device comprises a liquid crystal display device.

13. A microprocessor controlled apparatus as claimed in claim 1 wherein the means for maintaining the signals maintains the address signals on the sub-set of address lines for a predetermined period of time sufficiently long for the device to read the signals.

14. A method of transmitting data information from a first electrical device to a second electrical device comprising steps of:

sending signals from the first device to the second device through a sub-set of first device dedicated address lines that convey only address information, the sub-set being less than a total number of the first device address lines;

maintaining the signals constant on all of the individual sub-set lines for a predetermined period of time while signals on other address lines of the first device change, wherein the signals on the sub-set lines are held at a constant level over the predetermined period of time to permit the signals to be written into the second device; and

, in the second device,

interpreting the signals that are written into the device as data information, and not as address information.

15. In a data processing system having a memory comprised of a plurality of addressable storage locations for storing executable instructions, a digital data processor having a port comprised of a set of signal lines for outputting memory address signals for specifying individual ones of the addressable storage locations, and at least one device having a port comprised of at least one data signal line for inputting data, a method for inputting data to the device, comprising:

coupling a sub-set of the signal line set to the at least one data signal line;

executing, with the digital data processor, a plurality of instructions; and

during the execution of the plurality of instructions, triggering the device to input, on the at least one data signal line, the memory address signals that are output on the sub-set of the signal line set.

16. A method as set forth in claim 15, wherein the plurality of instructions are predeterminally stored in the memory such that the memory address signals that appear on the sub-set of the signal line set, during the execution of the plurality of instructions, remain constant.

17. A method as set forth in claim 15, wherein the memory stores a plurality of instruction sets each of which is comprised of a plurality of instructions, wherein individual ones of the plurality of instruction sets are aligned to a memory address boundary such that the memory address signals that appear on the sub-set of the signal line set, during the execution of the plurality of instructions, remain constant during the execution of instructions of a selected instruction set.

18. A method as set forth in claim 17, wherein an instruction set is selected for execution as a function of a value of data to be input to the device.

19. A method as set forth in claim 15, wherein the device includes a terminal for inputting a write signal, and wherein the step of triggering includes a step of activating the write signal during the execution of the plurality of instructions.

20. A method as set forth in claim 15, wherein the device includes a terminal for inputting a write signal, wherein the digital data processor includes a terminal for outputting a bit serial data signal, wherein the device write signal terminal is coupled to the processor bit serial data terminal, and wherein the step of triggering includes a step of activating the write signal during the execution of the plurality of instructions by outputting a predetermined bit serial data signal from the bit serial data terminal.

21. A data processing system, comprising:

a memory comprised of a plurality of addressable storage locations for storing executable instructions;

a digital data processor having a port comprised of a set of signal lines coupled to said memory for outputting memory address signals for specifying individual ones of the addressable storage locations; and

at least one device having a port comprised of data signal lines for inputting data, said data signal lines being coupled to a sub-set of the address signal line set;

wherein

said digital data processor executes a plurality of instructions and, during the execution of the plurality of instructions, said device is triggered to input, on said data signal lines, the memory address signals that are output on the sub-set of the address signal line set.

22. A data processing system as set forth in claim 21, wherein the plurality of instructions are predeterminally stored in the memory such that the memory address signals that appear on the sub-set of the signal line set, during the execution of the plurality of instructions, remain constant.

23. A data processing system as set forth in claim 21, wherein the memory stores a plurality of instruction sets each of which is comprised of a plurality of instructions, wherein individual ones of the plurality of instruction sets are aligned to a memory address boundary such that the memory address signals that appear on the sub-set of the signal line set, during the execution of the plurality of instructions, remain constant during the execution of instructions of a selected instruction set.

24. A data processing system as set forth in claim 21, wherein the device includes a terminal for inputting a write signal that is activated to write data appearing on the data signal lines into the device, wherein the digital data processor includes a terminal for outputting a bit serial data signal, wherein the device write signal terminal is coupled to the processor bit serial data terminal, and wherein the digital data processor includes means for activating the write signal during the execution of the plurality of instructions by outputting a predetermined bit serial data signal from the bit serial data terminal.

25. A data processing system as set forth in claim 21, wherein the memory stores a plurality of instruction sets each of which is comprised of a plurality of instructions, wherein individual ones of the plurality of instruction sets are aligned to a memory address boundary such that the memory address signals that appear on the sub-set of the signal line set, during the execution of the plurality of instructions, remain constant during the execution of instructions of a selected instruction set and have a value that ranges at least from 00 to 11.

26. A data processing system as set forth in claim 21, wherein said device is a display device for a radio telephone.

27. A data processing system as set forth in claim 26, wherein the plurality of instructions are predeterminally stored in the memory such that the memory address signals that appear on the sub-set of the signal line set, during the execution of the plurality of instructions, remain constant.

28. A data processing system as set forth in claim 26, wherein the memory stores a plurality of instruction sets each of which is comprised of a plurality of instructions, wherein individual ones of the plurality of instruction sets are aligned to a memory address boundary such that the memory address signals that appear on the sub-set of the signal line set, during the execution of the plurality of instructions, remain constant during the execution of instructions of a selected instruction set.

29. A data processing system as set forth in claim 26, wherein the device includes a terminal for inputting a write signal, and wherein the step of causing the device to input the memory address signals includes a step of activating the write signal during the execution of the plurality of instructions.

30. In a data processing system having a memory comprised of a plurality of addressable storage locations for storing executable instructions, a digital data processor having a port comprised of a set of signal lines for outputting memory address signals for specifying individual ones of the addressable storage locations, and at least one device having a port comprised of at least one data signal line for inputting data, a method for inputting data to the device, comprising:

coupling a sub-set of the signal line set to the at least one data signal line;

executing, with the digital data processor, a plurality of instructions; and

during the execution of the plurality of instructions, causing the device to input, on the at least one data signal line, the memory address signals that are output on the sub-set of the signal line set.

31. A data processing system, comprising:

a memory comprised of a plurality of addressable storage locations for storing executable instructions;

a digital data processor having a port comprised of a set of signal lines coupled to said memory for outputting memory address signals for specifying individual ones of the addressable storage locations; and

at least one device having a port comprised of data signal lines for inputting data, said data signal lines being coupled to a sub-set of the address signal line set;

wherein

said digital data processor executes a plurality of instructions and, during the execution of the plurality of instructions, said device is caused to input, on said data signal lines, the memory address signals that are output on the sub-set of the address signal line set.

32. A system as set forth in claim 31, wherein said device is a display device for a radio telephone.