Three-dimensional complementary field effect transistor process

• US 5,672,524 A
• Filed: 08/01/1995
• Issued: 09/30/1997
• Est. Priority Date: 08/01/1995
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Sun, Yu, Liu, Yowjuang W.
• Primary Examiner(s): Bowers, Jr., Charles L.
• Assistant Examiner(s): Radomsky, Leon
• Application Number:
  US08/509,911
• Time in Patent Office: 791 Days
• Field of Search: 437/40 RG, 437/40 GS, 437/41 RG, 437/41 GS, 437/203, 437/947, 437/981, 437/69, 437/44, 437/58, 148/DIG. 50, 148/DIG. 168, 257/330, 257/331, 257/332, 257/401, 257/622
• US Class Current: 438/270
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: Y10S 148/05 Etch and refill

Abstract

A field effect transistor has a short gate and is fabricated by: doping the bottom surface of a depression to form a relatively lightly doped region in the bottom of the depression; forming the gate of the field effect transistor on the sidewall of the depression such that the gate is insulated from the sidewall by a thin insulating layer; and implanting dopants to form the drain region and the source region of the transistor using the gate to mask a part of the relatively lightly doped region. The part of the relatively lightly doped region which is masked by the gate during implanting of the source and drain regions constitutes a lightly doped drain region of the transistor. The drain of the transistor is formed into the bottom of the depression. The length of the gate is primarily determined by the depth and/or profile of the sidewall. The source-to-drain on-resistance of the transistor is low because the transistor does not have a lightly doped source region. The transistor has high quality gate oxide because the sidewall of the depression upon which the gate oxide is grown is substantially free of ion impact damage.

Claims

1. A method, comprising:

growing a region of thermal oxide into a semiconductor material and thereby forming a first step and a second step in an upper surface of the semiconductor material, said first and said second steps each having a sloping sidewall surface wherein said sloping sidewall surface of said first step is steeper than said sloping sidewall surface of said second step;

removing the thermal oxide from said sidewall surfaces;

forming a gate insulating layer on said sloping sidewall surfaces of said first and said second steps; and

forming a gate of a transistor over the gate insulating layer such that a channel region of the transistor is disposed in the semiconductor material at said sloping sidewall surface of said first step.

2. A method comprising:

growing a region of thermal oxide in a semiconductor material so as to form a step in an upper surface of said semiconductor material, said step having a sidewall surface, wherein the upper surface comprises a first substantially lateral and planar surface, the sidewall surface, and a second substantially lateral and planar surface, the first surface being laterally and vertically displaced with respect to the second surface;

removing the thermal oxide from said sidewall surface;

forming a gate insulating layer on said sidewall surface;

forming a gate of a transistor over said gate insulating layer such that a channel region of said transistor is disposed in said semiconductor material at said sidewall surface;

forming a source region of the transistor in the semiconductor material at the second surface; and

forming a drain region of the transistor in the semiconductor material at the first surface, wherein said drain region is bounded in a lateral dimension by said source region of the transistor.

3. The method of claim 2, wherein an angle in a range of 120 to 90 degrees exists between the first surface and the sidewall surface, and wherein the region of thermal oxide has a thickness of at least 1500 angstroms.

4. The method of claim 2, wherein said gate comprises polycide.

5. A method, comprising:

growing a region of thermal oxide into a semiconductor material and thereby forming a depression into an upper surface of the semiconductor material, the depression having;

substantially parallel first and second sidewall surfaces formed in the semiconductor material,

substantially parallel third and fourth sidewall surfaces formed in the semiconductor material, wherein said first and said second sidewall surfaces have a steeper slope than said third and said fourth sidewall surfaces, and

a bottom surface;

removing the thermal oxide from the depression and from the sidewall surfaces;

forming a gate oxide on the first and second sidewall surfaces;

forming a first gate over the gate oxide on the first sidewall surface and forming a second gate over the gate oxide on the second sidewall surface;

forming a first source region and a second source region outside the depression; and

using the first and second gates as masks to form a drain region into the bottom surface, wherein said drain region is confined in a lateral dimension between said first and said second source regions.

6. The method of claim 5, wherein the using the first and second gates as masks further involves:

forming spacers along edges of the first and second gates such that both the gates and the spacers form the masks.

7. The method of claim 5, wherein the forming of the first gate and the second gate involves:

forming a layer of polycide; and

removing the layer of polycide except for that polycide disposed on said first and said second sidewall surfaces.

8. The method of claim 5, wherein an angle in a range of 120 to 90 degrees exists between each of said first and said second sidewall surfaces and the bottom surface, and wherein the thermal oxide in the region has a thickness of at least 1500 angstroms.

9. The method of claim 5, further comprising:

before the forming of the first and second gates, lightly doping a surface region of the semiconductor material in the bottom of the depression, the source and drain regions being formed by a relatively heavy doping with N type dopants.

10. The method of claim 5, further comprising:

before the growing of thermal oxide, defining the region of thermal oxide using a first layer of nitride and a second layer of nitride.

11. A method, comprising:

shaping multiple nitride layers on a semiconductor material;

performing a thermal oxidation step to form a depression into the semiconductor material, the depression having a first sloping sidewall surface and a second sloping sidewall surface, wherein said first sloping sidewall surface has a steeper slope than said second sloping sidewall surface;

removing thermal oxide from the depression and from the sidewall surfaces and forming a gate oxide on the sloping sidewall surfaces; and

forming a conductive layer over the depression and removing selected portions of the conductive layer such that gate structures remain along the first sloping sidewall surface but do not remain along the second sloping sidewall surface.

12. A method for forming a channel region of a field effect transistor, comprising:

forming a thin nitride layer overlying a semiconductor material;

forming a thick nitride layer which is separated from the thin nitride layer;

growing a thermal oxide into said semiconductor material using the thin and thick nitride layers as an oxidation mask to form a depression in said semiconductor material having a first sidewall surface and a second sidewall surface;

implanting first impurities into portions of said semiconductor material to form a doped region in said first and said second sidewall surfaces;

etching said thermal oxide from said depression and said first and said second sidewall surfaces;

implanting second impurities into said semiconductor material to form a lightly doped drain region in a bottom surface of said depression;

using said first sidewall surface of the depression as said channel region of said field effect transistor; and

implanting third impurities into said semiconductor material to form a heavily doped source region and to form a heavily doped drain region confined within said lightly doped drain region.

13. A method comprising:

forming a thin nitride layer vertically displaced above a semiconductor material;

forming a thick nitride layer which is separated in a vertical dimension from said thin nitride layer;

shaping said thin and thick nitride layers;

performing a thermal oxidation step to form a depression into said semiconductor material so as to form a first step and a second step in an upper surface of said semiconductor material, said first and said second steps each having a sloping sidewall surface, wherein said sloping sidewall surface of said first step is steeper than said sloping sidewall surface of said second step;

removing thermal oxide from the depression and said sloping sidewall surfaces of said first and said second steps and forming a gate insulating layer on said sloping sidewall surfaces of said first and said second steps; and

forming a gate of a transistor over said gate insulating layer such that a channel region of said transistor is disposed in said semiconductor material at said sloping sidewall surface of said first step.