Vertical channel silicon carbide metal-oxide-semiconductor field effect transistor with self-aligned gate for microwave and power applications, and method of making

• US 5,672,889 A
• Filed: 01/22/1996
• Issued: 09/30/1997
• Est. Priority Date: 03/15/1995
• Status: Expired due to Fees

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Brown, Dale Marius
• Primary Examiner(s): Crane, Sara W.
• Assistant Examiner(s): WILLE, DOUGLAS A
• Application Number:
  US08/589,672
• Time in Patent Office: 617 Days
• Field of Search: 257/77, 257/289, 257/508, 257/136, 257/330, 257/331, 257/332, 257/333, 257/334, 257/341, 257/260, 257/263, 257/266
• US Class Current: 257/77
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs

Abstract

A MOSFET includes a first SiC semiconductor contact layer, a SiC semiconductor channel layer supported by the first SiC contact layer, and a second SiC semiconductor contact layer supported by the channel layer. The second contact and channel layers are patterned to form a plurality of gate region grooves therethrough. Each of the gate region grooves includes a base surface and side surfaces which are covered with groove oxide material. A plurality of metal gate layers are provided, each being supported in a respective one of the plurality of grooves. A plurality of deposited oxide layers are provided, each in a respective one of the grooves so as to be supported by a respective one of the plurality of metal gate layers. A first metal contact layer is applied to the surface of the first SiC contact layer, and a second metal contact layer is applied to a portion of the surface of the second SiC contact layer.

Claims

1. A metal-oxide-semiconductor field effect transistor (MOSFET) comprising:

a first SiC semiconductor contact layer;

a SiC semiconductor channel layer supported by said first SiC semiconductor contact layer;

a second SiC semiconductor contact layer supported by said SiC semiconductor channel layer, said SiC semiconductor channel and second SiC semiconductor contact layers having a plurality of gate region grooves extending completely therethrough and having a base surface and side surfaces;

a plurality of metal gate layers, each one of said plurality of groove oxide layers covering the base surface and the side surfaces of a respective one of said plurality of gate region grooves;

a plurality of metal gate layers, each one of said plurality of metal gate layers being supported by a respective one of said plurality of groove oxide layers and having first and second surfaces, the first surface being situated on a plane above said first SiC semiconductor contact layer and the second surface being situated on a plane below said second SiC semiconductor contact layer;

a plurality of deposited oxide segments, each one of said plurality of deposited oxide segments being supported by a respective one of said plurality of metal gate layers and being substantially coplanar with said second SiC semiconductor contact layer;

a first metal contact layer situated on the surface of said first SiC semiconductor contact layer; and

a second metal contact layer situated on a portion of the surface of said second SiC semiconductor contact layer.

2. The MOSFET of claim 1, further comprising:

a surface oxide layer supported by said second metal contact layer, said surface oxide layer having first openings extending to said second metal contact layer and second openings extending through at least one of said plurality of deposited oxide segments to at least one of said plurality of metal gate layers;

a first contact pad situated on said surface oxide layer extending through at least one of said first openings to contact said second metal contact layer; and

a second contact pad extending through at least one of said second openings to contact at least one of said plurality of metal gate layers.

3. The MOSFET of claim 1, wherein at least one of said plurality of deposited oxide segments includes a conductive opening through which said second metal contact layer extends to contact a respective one of said plurality of metal gate layers, a portion of said second metal contact layer being in contact with said at least one conductive opening and being separate from another portion of said second metal contact layer.

4. The MOSFET of claim 1, wherein said first SiC semiconductor layer, said SiC semiconductor channel layer, and said second SiC semiconductor contact layer are all of the same conductivity type.