Vertical channel silicon carbide metal-oxide-semiconductor field effect transistor with self-aligned gate for microwave and power applications, and method of making
First Claim
1. A metal-oxide-semiconductor field effect transistor (MOSFET) comprising:
- a first SiC semiconductor contact layer;
a SiC semiconductor channel layer supported by said first SiC semiconductor contact layer;
a second SiC semiconductor contact layer supported by said SiC semiconductor channel layer, said SiC semiconductor channel and second SiC semiconductor contact layers having a plurality of gate region grooves extending completely therethrough and having a base surface and side surfaces;
a plurality of metal gate layers, each one of said plurality of groove oxide layers covering the base surface and the side surfaces of a respective one of said plurality of gate region grooves;
a plurality of metal gate layers, each one of said plurality of metal gate layers being supported by a respective one of said plurality of groove oxide layers and having first and second surfaces, the first surface being situated on a plane above said first SiC semiconductor contact layer and the second surface being situated on a plane below said second SiC semiconductor contact layer;
a plurality of deposited oxide segments, each one of said plurality of deposited oxide segments being supported by a respective one of said plurality of metal gate layers and being substantially coplanar with said second SiC semiconductor contact layer;
a first metal contact layer situated on the surface of said first SiC semiconductor contact layer; and
a second metal contact layer situated on a portion of the surface of said second SiC semiconductor contact layer.
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Accused Products
Abstract
A MOSFET includes a first SiC semiconductor contact layer, a SiC semiconductor channel layer supported by the first SiC contact layer, and a second SiC semiconductor contact layer supported by the channel layer. The second contact and channel layers are patterned to form a plurality of gate region grooves therethrough. Each of the gate region grooves includes a base surface and side surfaces which are covered with groove oxide material. A plurality of metal gate layers are provided, each being supported in a respective one of the plurality of grooves. A plurality of deposited oxide layers are provided, each in a respective one of the grooves so as to be supported by a respective one of the plurality of metal gate layers. A first metal contact layer is applied to the surface of the first SiC contact layer, and a second metal contact layer is applied to a portion of the surface of the second SiC contact layer.
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Citations
4 Claims
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1. A metal-oxide-semiconductor field effect transistor (MOSFET) comprising:
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a first SiC semiconductor contact layer; a SiC semiconductor channel layer supported by said first SiC semiconductor contact layer; a second SiC semiconductor contact layer supported by said SiC semiconductor channel layer, said SiC semiconductor channel and second SiC semiconductor contact layers having a plurality of gate region grooves extending completely therethrough and having a base surface and side surfaces; a plurality of metal gate layers, each one of said plurality of groove oxide layers covering the base surface and the side surfaces of a respective one of said plurality of gate region grooves; a plurality of metal gate layers, each one of said plurality of metal gate layers being supported by a respective one of said plurality of groove oxide layers and having first and second surfaces, the first surface being situated on a plane above said first SiC semiconductor contact layer and the second surface being situated on a plane below said second SiC semiconductor contact layer; a plurality of deposited oxide segments, each one of said plurality of deposited oxide segments being supported by a respective one of said plurality of metal gate layers and being substantially coplanar with said second SiC semiconductor contact layer; a first metal contact layer situated on the surface of said first SiC semiconductor contact layer; and a second metal contact layer situated on a portion of the surface of said second SiC semiconductor contact layer. - View Dependent Claims (2, 3, 4)
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Specification