Apparatus to decouple core circuits power supply from input-output circuits power supply in a semiconductor device package

• US 5,672,911 A
• Filed: 05/30/1996
• Issued: 09/30/1997
• Est. Priority Date: 05/30/1996
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Chou, Tai-Yu, Chakrabarti, Prabhansu, Patil, Sadanand R.
• Primary Examiner(s): Saadat, Mahshid D.
• Assistant Examiner(s): CLARK, SHEILA V
• Application Number:
  US08/655,599
• Time in Patent Office: 488 Days
• Field of Search: 257/691, 257/698, 257/700, 257/693, 257/697
• US Class Current: 257/691
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85424 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/85444 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/8547 Zirconium (Zr) as principal constituent
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/15173 in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A semiconductor device package for one or more semiconductor dice uses a package substrate having one pair of biplanar conductive planes and another pair of biplanar conductive planes. The pairs of planes are positioned in a coplanar relationship between the top traces and the bottom traces. Power may be supplied to die core circuits through one pair of planes and to die input-output circuits through another pair of planes to decouple the core circuits from the input-output circuits and minimize noise induced false switching in either set of circuits. The core circuits and the input-output circuits may be powered by the same power supply or separate power supplies.

Claims

1. A semiconductor device assembly, comprising:

a package substrate comprising a top surface, a bottom surface, first and second conductive patterns, and first, second and third dielectric layers,

the first dielectric layer disposed between the top surface and the first conductive pattern, the second dielectric layer disposed between the first and second conductive patterns, and the third dielectric layer disposed between the second conductive pattern and the bottom surface,

the bottom surface having a plurality of first external connectors, a plurality of second external connectors, a plurality of third external connectors, a plurality of fourth external connectors, and a plurality of signal external connectors,

the first conductive pattern having a first plane and a third plane, the first plane connected to the plurality of first external connectors, and the third plane connected to the plurality of third external connectors,

the second conductive pattern having a second plane and a fourth plane, the second plane connected to the plurality of second external connectors, and the fourth plane connected to the plurality of fourth external connectors, the first and second planes positioned in a biplanar relationship for forming an electrical capacitance, and the third and fourth planes positioned in a biplanar relationship for forming an electrical capacitance; and

a semiconductor die having core circuits and input-output circuits, said semiconductor die located on the top surface of said package substrate, said semiconductor die comprising;

a plurality of first power bond pads for the core circuits, the plurality of first power bond pads connected to the first plane,

a plurality of second power bond pads for the core circuits, the plurality of second power bond pads connected to the second plane,

a plurality of third power bond pads for the input-output circuits, the plurality of third power bond pads connected to the third plane,

a plurality of fourth power bond pads for the input-output circuits, the plurality of fourth power bond pads connected to the fourth plane, thereby decoupling the core circuits of said semiconductor die from the input-output circuits of said semiconductor die, and

a plurality of signal bond pads, the plurality of signal bond pads connected to the plurality of signal external connectors of said package substrate.

2. The semiconductor device assembly according to claim 1 wherein the first, second and third dielectric layers of said package substrate are epoxy.

3. The semiconductor device assembly according to claim 1 wherein the first, second and third dielectric layers of said package substrate are polyimide.

4. The semiconductor device assembly according to claim 1 wherein the first, second and third dielectric layers of said package substrate are fiberglass reinforced plastic.

5. The semiconductor device assembly according to claim 1 wherein the first, second and third dielectric layers of said package substrate are ceramic.

6. The semiconductor device assembly according to claim 1 wherein the external connectors are pins.

7. The semiconductor device assembly according to claim 1 wherein the external connectors are solder ball bumps.

8. The semiconductor device assembly according to claim 1 wherein the third plane encircles the first plane, and the fourth plane encircles the second plane.

9. The semiconductor device assembly according to claim 1 further comprising:

at least one chip capacitor having one terminal and an other terminal, the one terminal connected to the first plane of said package substrate, and the other terminal connected to the second plane of said package substrate.

10. The semiconductor device assembly according to claim 1 further comprising:

at least one chip capacitor having one terminal and an other terminal, the one terminal connected to the third plane of said package substrate, and the other terminal connected to the fourth plane of said package substrate.

11. The semiconductor device assembly according to claim 1 wherein said semiconductor die is a plurality of semiconductor dice.

12. The semiconductor device assembly according to claim 1 wherein the plurality of first external connectors is adapted for connection to a first voltage, the plurality of second external connectors is adapted for connection to a second voltage, the plurality of third external connectors is adapted for connection to a third voltage, and the plurality of fourth external connectors is adapted for connection to a fourth voltage, the first and second voltages derived from a first power supply, and the third and fourth voltages derived from a second power supply.

13. The semiconductor device assembly according to claim 12 wherein the voltage at the plurality of first external connectors is a negative voltage and the voltage at the plurality of second external connectors is a positive voltage with respect to the voltage at the plurality of first external connectors, and the voltage at the plurality of third external connectors is a negative voltage and the voltage at the plurality of fourth external connectors is a positive voltage with respect to the voltage at the plurality of third external connectors.

14. The semiconductor device assembly according to claim 13 wherein the first voltage of the first power supply and the third voltage of the second power supply are connected together.

15. The semiconductor device assembly according to claim 12 wherein the voltage at the plurality of first external connectors is a positive voltage and the voltage at the plurality of second external connectors is a negative voltage with respect to the voltage at the plurality of first external connectors, and the voltage at the plurality of third external connectors is a positive voltage and the voltage at the plurality of fourth external connectors is a negative voltage with respect to the voltage at the plurality of third external connectors.

16. The semiconductor device assembly according to claim 15 wherein the second voltage of the first power supply and the fourth voltage of the second power supply are connected together.

17. The semiconductor device assembly according to claim 12 wherein the voltage difference between the plurality of first external connectors and the plurality of second external connectors is from 4.5 volts to 5.5 volts.

18. The semiconductor device assembly according to claim 17 wherein the voltage difference between the plurality of third external connectors and the plurality of fourth external connectors is from 4.5 volts to 5.5 volts.

19. The semiconductor device assembly according to claim 17 wherein the voltage difference between the plurality of third external connectors and the plurality of fourth external connectors is from 2.5 volts to 4.0 volts.

20. A package substrate for a semiconductor die having core circuits, input-output circuits, a first plurality and a second plurality of power bond pads for the core circuits, a third plurality and a fourth plurality of power bond pads for the input-output circuits, and a plurality of signal bond pads, the package substrate comprising:

a top surface, a bottom surface, first and second conductive patterns, and first, second and third dielectric layers;

the first dielectric layer disposed between the top surface and the first conductive pattern, the second dielectric layer disposed between the first and second conductive patterns, and the third dielectric layer disposed between the second conductive pattern and the bottom surface;

the top surface having a plurality of first traces for connecting to the first plurality of power bond pads, a plurality of second traces for connecting to the second plurality of power bond pads, a plurality of third traces for connecting to the third plurality of power bond pads, a plurality of fourth traces for connecting to the fourth plurality of power bond pads, and a plurality of signal traces for connecting to the plurality of signal bond pads;

the bottom surface having a plurality of first external connectors, a plurality of second external connectors, a plurality of third external connectors, a plurality of fourth external connectors, and a plurality of signal external connectors;

the first conductive pattern having a first plane and a third plane, the first plane connected to the plurality of first traces and the plurality of first external connectors, and the third plane connected to the plurality of third traces and the plurality of third external connectors;

the second conductive pattern having a second plane and a fourth plane, the second plane connected to the plurality of second traces and the plurality of second external connectors, and the fourth plane connected to the plurality of fourth traces and the plurality of fourth external connectors, the first and second planes positioned in a biplanar relationship for forming an electrical capacitance, and the third and fourth planes positioned in a biplanar relationship for forming an electrical capacitance thereby decoupling the core circuits of said semiconductor die from the input-output circuits of said semiconductor die; and

the plurality of signal traces connected to the plurality of signal external connectors.

21. A semiconductor device assembly, comprising:

a semiconductor die having core circuits and input-output circuits, said semiconductor die having

at least one first power bond pad for the core circuits,

at least one second power bond pad for the core circuits,

at least one third power bond pad for the input-output circuits,

at least one fourth power bond pad for the input-output circuits, and

a plurality of signal bond pads;

a package substrate having first, second, third and fourth conductive patterns, first, second and third dielectric layers, at least one each of a first, second, third and fourth top vias, at least one each of a first, second, third and fourth bottom vias, a plurality of signal vias, at least one each of a first, second, third and fourth external connectors, a plurality of signal external connectors, and a top surface,

the first dielectric layer disposed between the first and second conductive patterns, the second dielectric layer disposed between the second and third conductive patterns, and the third dielectric layer disposed between the third and fourth conductive patterns,

the top surface of said package substrate defined by the first dielectric layer and the first conductive pattern disposed thereon, said semiconductor die located adjacent to the top surface;

the first conductive pattern of said package substrate comprising

an at least first top trace for connecting the at least one first power bond pad to the at least one first top via,

an at least second top trace for connecting the at least one second power bond pad, to the at least one second top via,

an at least third top trace for connecting the at least one third bond pad to the at least one third top via,

an at least fourth top trace for connecting the at least one fourth power bond pad to the at least one fourth top via, and

a plurality of top signal traces for connecting the plurality of signal bond pads to the plurality of signal vias;

the second conductive pattern of said package substrate comprising at least one each of a first and third planes, the at least one first plane connected to the at least one first top via and the at least one first bottom via, and the at least one third plane connected to the at least one third top via and the at least one third bottom via;

the third conductive pattern of said package substrate comprising at least one each of a second and fourth planes,

the at least one second plane connected to the at least one second top via and the at least one second bottom via, and the at least one fourth plane connected to the at least one fourth top via and the at least one fourth bottom via,

the first and second planes positioned in a biplanar relationship for forming an electrical capacitance,

the third and fourth planes positioned in a biplanar relationship for forming an electrical capacitance; and

the fourth conductive pattern of said package substrate comprising

an at least one first bottom trace for connecting the at least one first bottom via to the at least one first external connector,

an at least one second bottom trace for connecting the at least one second bottom via to the at least one second external connector,

an at least one third bottom trace for connecting the at least one third bottom via to the at one third external connector,

an at least one fourth bottom trace for connecting the at least one fourth bottom via to the at least one fourth external connector, and

a plurality of bottom signal traces for connecting the plurality of signal vias to the plurality of signal external connectors,

thereby decoupling the core circuits of said semiconductor die from the input-output circuits of said semiconductor die.