Charge pump circuit for high side switch

• US 5,672,992 A
• Filed: 04/11/1995
• Issued: 09/30/1997
• Est. Priority Date: 04/11/1995
• Status: Expired due to Term

• Current Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Nadd, Bruno C.
• Primary Examiner(s): CUNNINGHAM, TERRY D
• Application Number:
  US08/420,301
• Time in Patent Office: 903 Days
• Field of Search: 327/108, 327/389, 327/390, 327/391, 327/427, 327/434, 327/437, 327/534, 327/536, 327/537, 327/589
• US Class Current: 327/390
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 17/168 in composite switches
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

A high side monolithic switching circuit integrated into a silicon chip is described in which the charge pump is connected to the ground terminal by a constant current circuit and floats relative to the ground terminal to reduce noise generation. The charge pump is connected to a V_cc terminal by an auxiliary power MOSFET having its gate connected to the charge pump output circuit. The conventional charge pump diodes are implemented as MOSFET devices which can be easily integrated into the common monolithic chip. A clamping circuit across the charge pump permits the use of a low voltage, small area capacitor for a high voltage device.

Claims

1. A high side switch circuit comprising, in combination:

a gate controlled M0S power semiconductor device having first and second power electrodes and a control electrode;

a charge pump circuit having first and second power terminals and an output terminal;

a constant current source circuit having input and output terminals;

a V_cc input voltage terminal connected to said first power electrode of said gate controlled MOS power semiconductor device and connectable to a source of power;

a load terminal connected to said second power electrode of said gate controlled MOS power semiconductor device and connectable to a grounded load that is capable of being energized from said source of power when said gate controlled MOS power semiconductor device is closed; and

a ground terminal connectable to said grounded load;

said charge pump circuit being operable to produce an output voltage at its said output terminal which is higher than said V_cc input voltage;

said first power terminal of said charge pump circuit being connected with said V_cc input voltage terminal;

said second power terminal of said charge pump circuit connected to said input terminal of said constant current circuit;

said output terminal of said constant current circuit connected to said ground terminal, whereby said second power terminal has a floating potential and the currents at said V_cc input voltage terminal and at said ground terminal are constant so that noise at said V_cc input terminal and at said ground terminal is reduced;

said output terminal of said charge pump circuit being connected to said control electrode of said gate controlled MOS power semiconductor device for providing, in conjunction with said constant current source sinking current from said charge pump, a voltage sufficiently higher than the voltage of said second terminal to turn on said gate controlled MOS power semiconductor device.

2. The circuit of claim 1 wherein said gate controlled MOS power semiconductor device is a power MOSFET.

3. The circuit of claim 1 which further includes voltage clamp means connected between said first and second power terminals of said charge pump circuit to limit the voltage therebetween.

4. The circuit of claim 3 wherein said voltage clamp means comprises a zener diode.

5. The circuit of claim 1 wherein said charge pump circuit comprises, in combination:

a square wave oscillator connected to and operated from said first and second power terminals of said charge pump circuit and having an oscillator output terminal, an inverter buffer connected to said oscillator output terminal, a charge storage capacitor, a first diode and a second diode;

said inverter buffer having an output connected in series with said capacitor and said first diode to said control electrode of said gate controlled MOS power device;

said second diode connected from said V_cc input voltage terminal to the node between said capacitor and said first diode whereby, when the output of said inverter buffer is low, said capacitor is charged from the voltage at said V_cc terminal and through said second diode and, when said output of said inverter buffer is high, the voltage of said capacitor plus the voltage of said V_cc terminal are applied in series through said first diode to said control terminal of said gate controlled MOS power device.

6. The circuit of claim 5 which further includes voltage clamp means connected between said first and second power terminals of said charge pump circuit to limit the voltage therebetween.

7. The circuit of claim 6 wherein said voltage clamp means comprises a zener diode.

8. The circuit of claim 3 wherein said charge pump circuit comprises, in combination:

a square wave oscillator connected to and operated from said first and second power terminals of said charge pump circuit and having an oscillator output terminal, an inverter buffer connected to said oscillator output terminal, a charge storage capacitor, a first diode and a second diode;

said inverter buffer having an output connected in series with said capacitor and said first diode to said control electrode of said gate controlled MOS power device;

said second diode connected from said V_cc input voltage terminal to the node between said capacitor and said first diode whereby, when the output of said inverter buffer is low, said capacitor is charged from the voltage at said V_cc terminal and through said second diode and, when said output of said inverter buffer is high, the voltage of said capacitor plus the voltage of said V_cc terminal are applied in series through said first diode to said control terminal of said gate controlled MOS power device.

9. The circuit of claim 1 wherein said gate controlled MOS power semiconductor device, said charge pump circuit, and said current source are integrated into a monolithic semiconductor chip.

10. The circuit of claim 1 wherein said charge pump circuit comprises, in combination, a square wave oscillator connected to and operated from said first and second power terminals of said charge pump circuit, an oscillator output terminal, an inverter buffer connected to said oscillator output terminal, and a charge storage capacitor;

said inverter buffer having an output connected to said capacitor;

a first coupling circuit means coupling said capacitor to said control electrode of said gate controlled MOS power semiconductor device;

a second coupling circuit means for coupling said V_cc input voltage terminal to the node between said capacitor and said first coupling circuit means whereby, when the output of said inverter buffer is low, said capacitor is charged from the voltage at said V_cc terminal and through said second coupling means and, when said output of said inverter buffer is high, the voltage of said capacitor plus the voltage of said V_cc terminal are applied in series through said first coupling means to said control terminal of said gate controlled MOS power semiconductor device.

31. The circuit of claim 10 wherein said second coupling circuit means includes a control MOSFET.

11. A high side switch circuit comprising, in combination:

a gate controlled MOS power semiconductor device having first and second power electrodes and a control electrode;

a charge pump circuit having first and second power terminals and an output terminal;

a constant current source circuit having input and output terminals;

a V_cc input voltage terminal connected to said first power electrode of said gate controlled MOS power semiconductor device and connectable to a source of power;

a load terminal connected to said second power electrode of said gate controlled MOS power semiconductor device and connectable to a grounded load that is capable of being energized from said source of power when said gate controlled MOS power semiconductor device is closed;

a ground terminal connectable to said grounded load;

said charge pump circuit being operable to produce an output voltage at its said output terminal which is higher than said V_cc input voltage;

said first power terminal of said charge pump circuit being connected with said V_cc input voltage terminal;

said second power terminal of said charge pump circuit connected to said input terminal of said constant current circuit;

said output terminal of said constant current circuit connected to said ground terminal, whereby said second power terminal has a floating potential and the currents at said V_cc input voltage terminal and at said ground terminal are constant so that noise at said V_cc input terminal and at said ground terminal is reduced;

said output terminal of said charge pump circuit being connected to said control electrode of said gate controlled MOS power semiconductor device for providing a voltage sufficiently higher than the voltage of said second terminal to turn on said gate controlled MOS power semiconductor device; and

first switching means operable to connect and disconnect said charge pump first power terminal to said V_cc input voltage terminal and second switching means for connecting and disconnecting said control electrode of said gate controlled MOS power device to said ground terminal when said first switching means disconnects and connects said pump first power terminal to said V_cc input terminal respectively.

12. The circuit of claim 11 wherein said gate controlled MOS power semiconductor device, said charge pump circuit, said first switching means and said current source are integrated into a monolithic semiconductor chip.

13. The circuit of claim 11 wherein said gate controlled MOS power semiconductor device, said charge pump circuit, said voltage clamp means and said current source are integrated into a monolithic semiconductor chip.

14. A high side switch circuit comprising, in combination:

a gate controlled MOS power semiconductor device having first and second power electrodes and a control electrode;

a charge pump circuit having first and second power terminals and an output terminal;

a constant current source circuit having input and output terminals;

a V_cc input voltage terminal connected to said first power electrode of said gate controlled MOS power semiconductor device and connectable to a source of power;

a load terminal connected to said second power electrode of said gate controlled MOS power semiconductor device and connectable to a grounded load that is capable of being energized from said source of power when said gate controlled MOS power semiconductor device is closed;

a ground terminal connectable to said grounded load;

said charge pump circuit being operable to produce an output voltage at its said output terminal which is higher than said V_cc input voltage;

said first power terminal of said charge pump circuit being connected with said V_cc input voltage terminal;

said second power terminal of said charge pump circuit connected to said input terminal of said constant current circuit;

said output terminal of said constant current circuit connected to said ground terminal, whereby said second power terminal has a floating potential and the currents at said V_cc input voltage terminal and at said ground terminal are constant so that noise at said V_cc input terminal and at said ground terminal is reduced;

said output terminal of said charge pump circuit being connected to said control electrode of said gate controlled MOS power semiconductor device for providing a voltage sufficiently higher than the voltage of said second terminal to turn on said gate controlled MOS power semiconductor device;

voltage clamp means connected between said first and second power terminals of said charge pump circuit to limit the voltage therebetween; and

first switching means operable to connect and disconnect said charge pump first power terminal to said V_cc input voltage terminal and second switching means for connecting and disconnecting said control electrode of said gate controlled MOS power device to said ground terminal when said first switching means disconnects and connects said pump first power terminal to said V_cc input terminal respectively.

15. A high side switch circuit comprising, in combination:

a gate controlled MOS power semiconductor device having first and second power electrodes and a control electrode;

a charge pump circuit having first and second power terminals and an output terminal;

a constant current source circuit having input and output terminals;

a V_cc input voltage terminal connected to said first power electrode of said gate controlled MOS power semiconductor device and connectable to a source of power;

a load terminal connected to said second power electrode of said gate controlled MOS power semiconductor device and connect and connectable to a grounded load that is capable of being energized from said source of power when said gate controlled MOS power semiconductor device is closed;

a ground terminal connectable to said grounded load;

said charge pump circuit being operable to produce an output voltage at its said output terminal which is higher than said V_cc input voltage;

said first power terminal of said charge pump circuit being connected with said V_cc input voltage terminal;

said second power terminal of said charge pump circuit connected to said input terminal of said constant current circuit;

said output terminal of said constant current circuit connected to said ground terminal, whereby said second power terminal has a floating potential and the currents at said v_cc input voltage terminal and at said ground terminal are constant so that noise at said V_cc input terminal and at said ground terminal is reduced;

said output terminal of said charge pump circuit being connected to said control electrode of said gate controlled MOS power semiconductor device for providing a voltage sufficiently higher than the voltage of said second terminal to turn on said gate controlled MOS power semiconductor device; and

first switching means operable to connect and disconnect said charge pump first power terminal to said V_cc input voltage terminal and second switching means for connecting and disconnecting said control electrode of said gate controlled MOS power device to said ground terminal when said first switching means disconnects and connects said pump first power terminal to said V_cc input terminal respectively;

wherein said charge pump circuit comprises, in combination;

a square wave oscillator connected to and operated from said first and second power terminals of said charge pump circuit and having an oscillator output terminal, an inverter buffer connected to said oscillator output terminal, a charge storage capacitor, a first diode and a second diode;

said inverter buffer having an output connected in series with said capacitor and said first diode to said control electrode of said gate controlled MOS power device;

said second diode connected from said V_cc input voltage terminal to the node between said capacitor and said first diode whereby, when the output of said inverter buffer is low, said capacitor is charged from the voltage at said V_cc terminal and through said second diode and, when said output of said inverter buffer is high, the voltage of said capacitor plus the voltage of said V_cc terminal are applied in series through said first diode to said control terminal of said gate controlled MOS power device.

16. A high side switch circuit comprising, in combination:

a gate controlled MOS power semiconductor device having first and second power electrodes and a control electrode;

a charge pump circuit having first and second power terminals and an output terminal;

a constant current source circuit having input and output terminals;

a V_cc input voltage terminal connected to said first power electrode of said gate controlled MOS power semiconductor device and connectable to a source of power;

a load terminal connected to said second power electrode of said gate controlled MOS power semiconductor device and connectable to a grounded load that is capable of being energized from said source of power when said gate controlled MOS power semiconductor device is closed; and

a ground terminal connectable to said grounded load;

said charge pump circuit being operable to produce an output voltage at its said output terminal which is higher than said V_cc input voltage;

said first power terminal of said charge pump circuit being connected with said V_cc input voltage terminal;

said second power terminal of said charge pump circuit connected to said input terminal of said constant current circuit;

said output terminal of said constant current circuit connected to said ground terminal, whereby said second power terminal has a floating potential and the currents at said V_cc input voltage terminal and at said ground terminal are constant so that noise at said V_cc input terminal and at said ground terminal is reduced;

said output terminal of said charge pump circuit being connected to said control electrode of said gate controlled MOS power semiconductor device for providing a voltage sufficiently higher than the voltage of said second terminal to turn on said gate controlled MOS power semiconductor device; and

wherein said constant current circuit comprises a first control MOSFET having drain and source electrodes connected to said second power terminal of said charge pump circuit and said ground terminal respectively and a cascaded enhancement mode MOSFET and depletion mode MOSFET connected between an auxiliary voltage source and said ground terminal;

the node between said enhancement mode and depletion mode MOSFETs connected to their respective gates and to the gate of said first control MOSFET.

17. The circuit of claim 16 which further includes a second control MOSFET in combination with said first MOSFET to increase the voltage between said second power terminal of said charge pump circuit and said ground terminal without breakdown of said first control MOSFET.

18. The circuit of claim 16 which further includes voltage clamp means connected between said first and second power terminals of said charge pump circuit to limit the voltage therebetween.

19. The circuit of claim 17 which further includes voltage clamp means connected between said first and second power terminals of said charge pump circuit to limit the voltage therebetween.

20. The circuit of claim 18 wherein said voltage clamp means comprises a zener diode.

21. The circuit of claim 19 wherein said voltage clamp means comprises a zener diode.

22. The circuit of claim 17 wherein said charge pump circuit comprises, in combination:

a square wave oscillator connected to and operated from said first and second power terminals of said charge pump circuit and having an oscillator output terminal, an inverter buffer connected to said oscillator output terminal, a charge storage capacitor, a first diode and a second diode;

said inverter buffer having an output connected in series with said capacitor and said first diode to said control electrode of said gate controlled MOS power device;

said second diode connected from said V_cc input voltage terminal to the node between said capacitor and said first diode whereby, when the output of said inverter buffer is low, said capacitor is charged from the voltage at said V_cc terminal and through said second diode and, when said output of said inverter buffer is high, the voltage of said capacitor plus the voltage of said V_cc terminal are applied in series through said first diode to said control terminal of said gate controlled MOS power device.

23. A high side switch circuit comprising, in combination:

a gate controlled MOS power semiconductor device having first and second power electrodes and a control electrode;

a charge pump circuit having first and second power terminals and an output terminal;

a constant current source circuit having input and output terminals;

a V_cc input voltage terminal connected to said first power electrode of said gate controlled MOS power semiconductor device and connectable to a source of power;

a load terminal connected to said second power electrode of said gate controlled MOS power semiconductor device and connectable to a grounded load that is capable of being energized from said source of power when said gate controlled MOS power semiconductor device is closed;

a ground terminal connectable to said grounded load;

said charge pump circuit being operable to produce an output voltage at its said output terminal which is higher than said V_cc input voltage;

said first power terminal of said charge pump circuit being connected with said V_cc input voltage terminal;

said second power terminal of said charge pump circuit connected to said input terminal of said constant current circuit;

said output terminal of said constant current circuit connected to said ground terminal, whereby said second power terminal has a floating potential and the currents at said V_cc input voltage terminal and at said ground terminal are constant so that noise at said V_cc input terminal and at said ground terminal is reduced;

said output terminal of said charge pump circuit being connected to said control electrode of said gate controlled MOS power semiconductor device for providing a voltage sufficiently higher than the voltage of said second terminal to turn on said gate controlled MOS power semiconductor device;

add an auxiliary power MOSFET having first and second power terminals and a gate terminal;

said first and second power terminals of said auxiliary power MOSFET connected to said first power terminal of said charge pump circuit and said V_cc input voltage terminal respectively;

said gate terminal of said auxiliary power MOSFET connected to said control electrode-of said gate controlled MOS power semiconductor device.

24. The circuit of claim 23 which further includes starter circuit means coupled between a auxiliary supply voltage source and said charge pump circuit for starting said charge pump circuit before said auxiliary power MOSFET conducts.

25. The circuit of claim 23 wherein said gate controlled MOS power semiconductor device, said charge pump circuit, said auxiliary power MOSFET and said current source are integrated into a monolithic semiconductor chip.

26. A high side switch circuit comprising, in combination:

a gate controlled MOS power semiconductor device having first and second power electrodes and a control electrode;

a charge pump circuit having first and second power terminals and an output terminal;

a V_cc input voltage terminal connected to said first power electrode of said gate controlled MOS power semiconductor device and connectable to a source of power;

a load terminal connected to said second power electrode of said gate controlled MOS power semiconductor device and connectable to a grounded load which, when said grounded load is connected to said load terminal and said V_cc input is connected to said source of power, is energized from said source of power when said gate controlled MOS power semiconductor device is closed; and

a ground terminal connectable to said grounded load;

said charge pump circuit being operable to produce an output voltage at its said output terminal which is higher than said V_cc input voltage;

said second power terminal of said charge pump circuit connected to said ground terminal, whereby said output terminal of said charge pump circuit is connected to said control electrode of said gate controlled MOS power semiconductor device for providing a voltage sufficiently higher than the voltage of said second terminal to turn on said gate controlled MOS power semiconductor device;

a grounding switch connected to said control electrode of said MOS gated power device for grounding said control electrode when said grounding switch is closed; and

an auxiliary power MOSFET having first and second power terminals and a gate terminal;

said first and second power terminals of said auxiliary power MOSFET connected to said first power terminal of said charge pump circuit and said V_cc input voltage terminal respectively;

said gate terminal of said auxiliary power MOSFET connected to said control electrode of said gate controlled MOS power semiconductor device so that when said grounding switch is closed, said gate terminal of said auxiliary power MOSFET is grounded, thereby turning off said auxiliary power MOSFET to entirely electrically isolate said charge pump circuit from said supply voltage.

27. A high side switch circuit comprising, in combination:

a gate controlled MOS power semiconductor device having first and second power electrodes and a control electrode;

a charge pump circuit having first and second power terminals and an output terminal;

a V_cc input voltage terminal connected to said first power electrode of said gate controlled MOS power semiconductor device and connectable to a source of power;

a load terminal connected to said second power electrode of said gate controlled MOS power semiconductor device and connectable to a grounded load which, when said grounded load is connected to said load terminal and said V_cc input is connected to said source of power, is energized from said source of power when said gate controlled MOS power semiconductor device is closed; and

a ground terminal connectable to said grounded load;

said charge pump circuit being operable to produce an output voltage at its said output terminal which is higher than said V_cc input voltage;

said second power terminal of said charge pump circuit connected to said ground terminal, whereby said output terminal of said charge pump circuit is connected to said control electrode of said gate controlled MOS power semiconductor device for providing a voltage sufficiently higher than the voltage of said second terminal to turn on said gate controlled MOS power semiconductor device;

a grounding switch connected to said control electrode of said MOS gated power device for grounding said control electrode when said grounding switch is closed;

an auxiliary power MOSFET having first and second power terminals and a gate terminal;

said first and second power terminals of said auxiliary power MOSFET connected to said first power terminal of said charge pump circuit and said V_cc input voltage terminal respectively;

said gate terminal of said auxiliary power MOSFET connected to said control electrode of said gate controlled MOS power semiconductor device so that when said grounding switch is closed, said gate terminal of said auxiliary power MOSFET is grounded, thereby turning off said auxiliary power MOSFET to electrically isolate said charge pump circuit from said supply voltage; and

starter circuit means coupled between an auxiliary supply voltage source and said charge pump circuit for starting said charge pump circuit before said auxiliary power MOSFET conducts.

28. A high side switch circuit comprising, in combination:

a gate controlled MOS power semiconductor device having first and second power electrodes and a control electrode;

a charge pump circuit having first and second power terminals and an output terminal;

a constant current source circuit having input and output terminals;

a V_cc input voltage terminal connected to said first power electrode of said gate controlled MOS power semiconductor device and connectable to a source of power;

a load terminal connected to said second power electrode of said gate controlled MOS power semiconductor device and connectable to a grounded load that is capable of being energized from said source of power when said gate controlled MOS power semiconductor device is closed;

a ground terminal connectable to said grounded load;

said charge pump circuit being operable to produce an output voltage at its said output terminal which is higher than said V_cc input voltage;

said first power terminal of said charge pump circuit being connected with said V_cc input voltage terminal;

said second power terminal of said charge pump circuit connected to said input terminal of said constant current circuit;

said output terminal of said constant current circuit connected to said ground terminal, whereby said second power terminal has a floating potential and the currents at said V_cc input voltage terminal and at said ground terminal are constant so that noise at said V_cc input terminal and at said ground terminal is reduced;

said output terminal of said charge pump circuit being connected to said control electrode of said gate controlled MOS power semiconductor device for providing a voltage sufficiently higher than the voltage of said second terminal to turn on said gate controlled MOS power semiconductor device;

wherein said charge pump circuit comprises, in combination, a square wave oscillator connected to and operated from said first and second power terminals of said charge pump circuit, an oscillator output terminal, an inverter buffer connected to said oscillator output terminal, and a charge storage capacitor;

said inverter buffer having an output connected to said capacitor;

a first coupling circuit means coupling said capacitor to said control electrode of said gate controlled MOS power semiconductor device;

a second coupling circuit means for coupling said V_cc input voltage terminal to the node between said capacitor and said first coupling circuit means whereby, when the output of said inverter buffer is low, said capacitor is charged from the voltage at said V_cc terminal and through said second coupling means and, when said output of said inverter buffer is high, the voltage of said capacitor plus the voltage of said V_cc terminal are applied in series through said first coupling means to said control terminal of said gate controlled MOS power semiconductor device; and

wherein said first coupling means comprises a depletion mode MOSFET having source and drain terminals connected to said capacitor and to said control electrode of said gate controlled MOS power semiconductor device respectively, said depletion mode MOSFET having a substrate diode connected to the output of said inverter buffer;

a resistive circuit means connected from said capacitor to the gate of said depletion mode MOSFET, and a second control MOSFET connected from said gate of said depletion mode MOSFET to said ground terminal and having a gate connected to said oscillator output terminal.

29. The circuit of claim 28 wherein said second coupling means is a diode.

30. The circuit of claim 28 wherein said resistive circuit means comprises a second depletion mode MOSFET having a gate connected to the gate of said first-mentioned depletion mode transistor and a substrate connected to the substrate of said first-mentioned depletion mode MOSFET.

32. The circuit of claim 28 wherein said second coupling circuit means includes a control MOSFET.