Antifuse circuit using standard MOSFET devices
First Claim
1. A method for selectively programming a field-effect transistor (FET) having channel, source, and drain regions formed in a semi-conductor layer with a characteristic source-drain breakdown voltage and resistivity, comprising the steps of:
- a) selecting the FET to be programmed; and
b) applying a programming voltage to the drain region, the programming voltage being greater than or equal to the source-drain breakdown voltage of the transistor and the resistivity of the transistor is reduced to about ten kilo-ohms.
1 Assignment
0 Petitions
Accused Products
Abstract
A programmable device is formed from a field-effect transistor. Specifically, the present invention generally related to integrated circuit (IC) structures and more particularly, to an improved antifuse structure for use in programming redundant and customizable IC chips. The anti-fuse is NFET made of MOS material and formed at a face of a semiconductor layer having an n-type doped source, and drain region, and a p-type doped channel region separating the source and drain regions. The device is programmed by applying a high voltage to the NFET drain to form a hot spot located along the channel width of the drain and thereby forming a bridge, which now has less resistance than the surrounding channel material, to the NFET source.
-
Citations
4 Claims
-
1. A method for selectively programming a field-effect transistor (FET) having channel, source, and drain regions formed in a semi-conductor layer with a characteristic source-drain breakdown voltage and resistivity, comprising the steps of:
-
a) selecting the FET to be programmed; and b) applying a programming voltage to the drain region, the programming voltage being greater than or equal to the source-drain breakdown voltage of the transistor and the resistivity of the transistor is reduced to about ten kilo-ohms. - View Dependent Claims (2, 3)
-
-
4. A method for selectively programming a field-effect transistor (FET) having channel, source, and drain regions formed in a semi-conductor layer with a characteristic source-drain breakdown voltage and resistivity, comprising the steps of:
-
a) selecting the FET to be programmed; and b) applying a programming voltage to the drain region, the programming voltage being greater than or equal to the source-drain breakdown voltage of the transistor and resistivity of the transistor is reduced to about one to ten kilo-ohms.
-
Specification