Antifuse circuit using standard MOSFET devices

• US 5,672,994 A
• Filed: 12/21/1995
• Issued: 09/30/1997
• Est. Priority Date: 12/21/1995
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Nowak, Edward Joseph, Tong, Minh Ho, Au, Wai-Ming William
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): ZWEIZIG, JEFFERY SHAWN
• Application Number:
  US08/576,026
• Time in Patent Office: 649 Days
• Field of Search: 327/525
• US Class Current: 327/525
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A programmable device is formed from a field-effect transistor. Specifically, the present invention generally related to integrated circuit (IC) structures and more particularly, to an improved antifuse structure for use in programming redundant and customizable IC chips. The anti-fuse is NFET made of MOS material and formed at a face of a semiconductor layer having an n-type doped source, and drain region, and a p-type doped channel region separating the source and drain regions. The device is programmed by applying a high voltage to the NFET drain to form a hot spot located along the channel width of the drain and thereby forming a bridge, which now has less resistance than the surrounding channel material, to the NFET source.

Claims

1. A method for selectively programming a field-effect transistor (FET) having channel, source, and drain regions formed in a semi-conductor layer with a characteristic source-drain breakdown voltage and resistivity, comprising the steps of:

a) selecting the FET to be programmed; and

b) applying a programming voltage to the drain region, the programming voltage being greater than or equal to the source-drain breakdown voltage of the transistor and the resistivity of the transistor is reduced to about ten kilo-ohms.

2. The method of claim 1, wherein the field-effect transistor is an NFET.

3. The method of claim 1, wherein during the step of applying a programming voltage a bias voltage is applied to the gate of the field-effect transistor.

4. A method for selectively programming a field-effect transistor (FET) having channel, source, and drain regions formed in a semi-conductor layer with a characteristic source-drain breakdown voltage and resistivity, comprising the steps of:

a) selecting the FET to be programmed; and

b) applying a programming voltage to the drain region, the programming voltage being greater than or equal to the source-drain breakdown voltage of the transistor and resistivity of the transistor is reduced to about one to ten kilo-ohms.