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Sub-problem extraction method for wiring localized congestion areas in VLSI wiring design

  • US 5,673,201 A
  • Filed: 03/21/1996
  • Issued: 09/30/1997
  • Est. Priority Date: 09/29/1992
  • Status: Expired due to Fees
First Claim
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1. A computer implementable method for wiring congested areas in a VLSI design following a failed global wiring attempt, comprising the steps ofdetecting a congested area containing one or more identified invalid net segments in the VLSI design using the output of a global wiring program which has produced the failed global wiring attempt and which output contains a listing of said one or more identified invalid net segments;

  • determining a bounding area for the congested area which is larger in size than said congested area;

    fixing perimeter attachment points at locations where wires cross the bounding area;

    extracting the bounding area and the perimeter attachment points as a sub-problem extraction area from the VLSI design;

    associating wiring parameters with the sub-problem extraction area;

    setting wire weights for the wiring parameters;

    wiring the sub-problem extraction area to derive a wired solution by;

    (a) attempting to wire the sub-problem extraction area in accordance with the wire weights,(b) in response to the wiring attempt completing unsuccessfully, changing at least one of the wire weights,(c) repeating sub-steps (a) and (b) until a wiring attempt completes successfully; and

    placing the wired solution for the sub-problem extraction area back into the VLSI design.

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