Word line voltage boosting circuit and method thereof
First Claim
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1. A word line voltage boosting circuit for a semiconductor memory device, comprising:
- a boosting circuit which boosts a word line voltage from a first voltage level to a second voltage level in response to an activation signal when less than a first predetermined number of word lines are activated;
a voltage adding circuit coupled to an output of said boosting circuit which further boosts said word line voltage to a third voltage level greater than said second voltage level in response to a mode operation signal, such that said voltage adding circuit is not operative to boost said word line voltage to said third voltage level until at least said first predetermined number of word lines are activated; and
a word line driving circuit coupled to said output of said boosting circuit and an output of said voltage adding circuit which supplies said boosted word line voltage having one of said second voltage level and said third voltage level to an output line.
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Abstract
A word line voltage boosting circuit varies a word line output voltage according to variation of the number of the word lines to be activated. A boosting circuit boosts a word line voltage which has been precharged to a first level voltage to a second level voltage in response to an activation signal. A voltage adding circuit further boosts the word line voltage to a third voltage level by adding a predetermined voltage to the second level voltage if the number of the word lines to be activated increases. A driving circuit includes a bootstrap circuit for stably providing the boosted word line voltage to an output line.
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9 Claims
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1. A word line voltage boosting circuit for a semiconductor memory device, comprising:
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a boosting circuit which boosts a word line voltage from a first voltage level to a second voltage level in response to an activation signal when less than a first predetermined number of word lines are activated; a voltage adding circuit coupled to an output of said boosting circuit which further boosts said word line voltage to a third voltage level greater than said second voltage level in response to a mode operation signal, such that said voltage adding circuit is not operative to boost said word line voltage to said third voltage level until at least said first predetermined number of word lines are activated; and a word line driving circuit coupled to said output of said boosting circuit and an output of said voltage adding circuit which supplies said boosted word line voltage having one of said second voltage level and said third voltage level to an output line. - View Dependent Claims (2, 3, 4, 5)
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6. An word line voltage boosting method of a semiconductor memory device, comprising:
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boosting a word line voltage from a first voltage level to a second voltage level in response to an activation signal when less than a first predetermined number of word lines are activated; further boosting said word line voltage to a third voltage level greater than said second voltage level in response to a mode operation signal, said word line voltage being prevented from being boosted to said third voltage level until at least said first predetermined number of word lines are activated; and supplying said boosted word line voltage having one of said second voltage level and said third voltage level to an output line. - View Dependent Claims (7, 8, 9)
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Specification