Dynamic random access memory

• US 5,673,229 A
• Filed: 03/08/1996
• Issued: 09/30/1997
• Est. Priority Date: 12/26/1990
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Okamura, Junichi, Furuyama, Tohru
• Primary Examiner(s): ZARABIAN, AMIR
• Application Number:
  US08/612,759
• Time in Patent Office: 571 Days
• Field of Search: 365/201, 365/226, 365/230.061, 365/189.09, 365/203, 365/230.08, 365/149, 307/449
• US Class Current: 365/201
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A dynamic random access memory includes a dynamic memory cell having a transfer N-channel MOS transistor and a capacitive element for storing data which is connected to the transfer N-channel MOS transistor, a word line connected to a gate of the transfer N-channel transistor, of the dynamic memory cell, and a word line driving voltage source, to which power voltage is input for raising the input power voltage to generate a word line driving voltage. Also, the dynamic random access memory includes an address circuit for generating internal address signals in accordance with externally input address signals, a word line selecting circuit for decoding the internal address signals and outputting a word line selecting signal which varies within a range between the word line driving voltage and a ground potential, and a word line driving circuit for driving a corresponding word line in accordance with the word line selecting signal, the word line driving circuit being provided in correspondence with the word line and having a P-channel MOS transistor which has a source connected to a first node having the word line driving voltage, a drain connected to the word line and a gate to which the word line selecting signal is applied.

Claims

1. A dynamic random access memory comprising:

a dynamic memory cell having a transfer N-channel MOS transistor and a capacitive element for storing data which is connected to the transfer N-channel MOS transistor;

a word line connected to a gate of the transfer N-channel MOS transistor of said dynamic memory cell;

a word line driving voltage source, to which power voltage is input for raising the input power voltage to generate a word line driving voltage, said word line driving voltage source being a voltage raising circuit for outputting a steady-level voltage as the word line driving voltage;

an address circuit for generating internal address signals in accordance with externally input address signals;

a word line selecting circuit, connected to said word line driving voltage source, for decoding the internal address signals, said word line selecting circuit including a precharge circuit and a discharge circuit serially connected between a first node and a ground potential node and outputting a word line selecting signal via a series-connection node connecting said precharge circuit and said discharge circuit, the word line selecting signal having a voltage which varies between a first voltage and a second voltage; and

a word line driving circuit for driving a corresponding word line in accordance with the word line selecting signal, said word line driving circuit being provided in correspondence with said word line and having a P-channel MOS transistor which has a source connected to the first node having the word line driving voltage, a drain connected to said word line and a gate to which the word line selecting signal is applied,

wherein said word line driving voltage source outputs the steady-level voltage during a first period in which said precharge circuit precharges the series-connection node and during a second period in which said word line driving circuit drives the corresponding word line.

2. A dynamic random access memory according to claim 1, wherein said precharge circuit is formed of a P-channel MOS transistor, connected between said first node and said discharge circuit and having a gate to which a precharge control signal is applied, for precharging the series-connection node, to be in an ON state while the precharge control signal is active and having a voltage equal to the word line driving voltage, said discharge circuit being formed of a plurality of N-channel MOS transistors for pulling down the series-connection node to a voltage equal to a ground potential, said discharge circuit being connected in series between said precharge circuit and said ground potential node, having gates to which the internal address signals are applied, and being in the ON state while predetermined internal address signals are input.

3. A dynamic random access memory according to claim 2, wherein said plurality of N-channel MOS transistors comprises three N-channel MOS transistors.

4. A dynamic random access memory according to claim 1, wherein said voltage raising circuit includes a clock signal generating circuit for generating a first clock signal and a second clock signal, a first charge pump circuit which receives the first clock signal, for performing a charge pump and supplying a charge pump output to a raised-voltage output node, and a second charge pump circuit which receives the second clock signal, for performing a charge pump and supplying a charge pump output to the raised-voltage output node.

5. A dynamic random access memory according to claim 1, wherein said address circuit is activated by the power voltage, and outputs the internal address signal which varies within a range between the power voltage and a ground voltage.

6. A dynamic random access memory according to claim 1, wherein the word line driving voltage is applied to a backgate of said P-channel MOS transistor for driving the corresponding word line.

7. A dynamic random access memory according to claim 1, wherein said word line driving circuit further comprises an N-channel MOS transistor for pull down, which is connected between a drain of said P-channel MOS transistor for driving the corresponding word line and a ground potential node, and having a gate to which said word line selecting signal is applied.

12. The semiconductor memory device according to claim 5, further comprising:

an address circuit for generating internal address signals in accordance with externally input address signals.

19. A dynamic random access memory according to claim 1, wherein the level of the first voltage is set to turn off the p-channel MOS transistor of said word line driving circuit, and the level of the second voltage is set to turn on the p-channel MOS transistor.

20. A dynamic random access memory according to claim 1, wherein the first voltage is word line driving voltage and the second voltage is ground potential.

8. A semiconductor memory device, comprising:

a word line connected to a plurality of dynamic memory cells;

a word line selecting circuit responsive to address signals, the word line selecting circuit including a precharge circuit and a discharge circuit serially connected between a node supplied with a word line driving potential and a terminal supplied with a ground potential, for generating a selection signal, the selection signal having the word line driving potential when the word line is not selected and the ground potential when the word line is selected, and outputting the selection signal via a series-connection node connecting said precharge circuit and said discharge circuit;

a word line driving voltage source connected to said word line selecting circuit for supplying the word line driving potential, said word line driving voltage source being a voltage raising circuit for outputting a steady-level voltage as the word line driving potential during a first period in which said precharge circuit precharges the series-connection node and during a second period; and

a word line driving circuit responsive to the selection signal, the word line driving circuit having a p-channel charging transistor and an n-channel discharging transistor, and being connected between the word line selecting circuit and the word line, and during the second period the word line driving circuit charging the word line to the word line driving potential with the p-channel charging transistor when the selection signal is at the ground potential and discharging the word line to the ground potential with the n-channel discharging transistor when the selection signal is at the word line driving potential.

9. The semiconductor memory device according to claim 8, wherein the n-channel discharging transistor and the p-channel charging transistor are connected in series.

14. The semiconductor memory device according to claim 8, wherein said voltage raising circuit includes a clock signal generating circuit for generating a first clock signal and a second clock signal, a first charge pump circuit which receives the first clock signal for performing a charge pump and supplying a charge pump output to a raised-voltage output node, and a second charge pump circuit which receives said second clock signal for performing a charge pump and supplying a charge pump output to the raised-voltage output node.

10. A semiconductor memory device, comprising:

a word line connected to a plurality of dynamic memory cells;

a word line driving potential source for supplying a word line driving potential at an output node, said word line driving potential source being a voltage raising circuit for outputting a steady-level voltage as the word line driving potential;

a word line selecting circuit having a first p-channel transistor, a first n-channel transistor, a second n-channel transistor, and a third n-channel transistor connected in series between the output node and a ground terminal, the word line selecting circuit providing a selection signal at a first connection node between the first p-channel transistor and the first n-channel transistor; and

a word line driving circuit connected to the first connection node of the word line selection circuit, having a second p-channel transistor and a fourth n-channel transistor connected in series between the output node, supplied with the word line driving potential when the word line is selected, and the ground terminal, a second connection node between the second p-channel transistor and the fourth n-channel transistor being connected to the word line,

wherein said word line driving potential source outputs the steady-level voltage for a first period in which said first p-channel transistor is in an ON state and a second period in which said second p-channel transistor is in an ON state.

11. The semiconductor memory device according to claim 10, further comprising:

an address circuit for generating internal address signals in accordance with externally input address signals.

13. The semiconductor memory device according to claim 10, wherein said voltage raising circuit includes a clock signal generating circuit for generating a first clock signal and a second clock signal, a first charge pump circuit which receives the first clock signal for performing a charge pump and supplying a charge pump output to a raised-voltage output node, and a second charge pump circuit which receives said second clock signal for performing a charge pump and supplying a charge pump output to the raised-voltage output node.

15. A dynamic random access memory comprising:

a dynamic memory cell having a transfer n-channel MOS transistor and a capacitive element for storing data which is connected to the transfer n-channel MOS transistor;

a word line connected to a gate of the transfer n-channel MOS transistor of said dynamic memory cell;

a charge pump circuit for receiving externally supplied power voltage and for generating an internal power supply voltage which is boosted up from the externally supplied power voltage, and outputting the internal power supply voltage as a steady-level voltage;

a decoder circuit which receives address signals and having a first p-channel MOS transistor for receiving the steady-level voltage for generating a word line selecting signal; and

a word line driving circuit for driving a corresponding word line in accordance with the word line selecting signal, said word line driving circuit being provided in correspondence with said word line and having a second p-channel MOS transistor and a first n-channel MOS transistor, said second p-channel and MOS transistor having a source connected to a first node having the steady-level voltage, a drain connected to said word line and a gate which is controlled in accordance with the word line selecting signal, said first n-channel MOS transistor having a drain connected to said second p-channel MOS transistor, a source connected to a ground terminal and a gate which is controlled in accordance with the word line selecting signal,

wherein said charge pump circuit outputs the steady-level voltage for a first period in which said first p-channel MOS transistor is in an ON state and a second period in which said second p-channel MOS transistor is in an on state.

16. A dynamic random access memory according to claim 15, wherein said charge pump circuit includes

a clock signal generating circuit for generating a first clock signal and a second clock signal,

a first charge pump circuit which receives the first clock signal for performing a charge pump and supplying a charge pump output to a raised voltage output node, and

a second charge pump circuit which receives the second clock signal for performing a charge pump and supplying a charge pump output to the raised voltage output node.

17. A dynamic random access memory according to claim 15, wherein said selecting signal is the steady-level voltage when the word line is not selected and ground potential when the word line is selected, and said word line driving circuit charges the word line to the steady-level voltage with said second p-channel MOS transistor when the selecting signal is the ground potential and discharges the word line to the ground potential with said first n-channel MOS transistor when the selecting signal is the steady-level voltage.

18. A dynamic random access memory according to claim 15, wherein said decoder circuit further includes a second n-channel MOS transistor, a third n-channel MOS transistor and a fourth n-channel MOS transistor connected in series between the first node and the ground terminal, said decoder circuit providing the word line selecting signal at a connection node between said first p-channel MOS transistor and said second n-channel MOS transistor.