Method and apparatus for identifying and controlling a target peripheral device in a multiple bus system

• US 5,673,400 A
• Filed: 06/07/1995
• Issued: 09/30/1997
• Est. Priority Date: 06/06/1995
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Kenny, John D.
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US08/478,579
• Time in Patent Office: 846 Days
• Field of Search: 395/306-309, 395/733, 395/741, 395/737, 395/281, 395/821, 395/868, 395/800
• US Class Current: 710/306
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence

Abstract

An apparatus and method for controlling devices in a multiple bus system such as a system having two or more ISA type buses. Separate ISA bus controllers may be provided for each ISA bus, linked on a common bus system such as a PCI bus. One ISA controller may be designated as a primary ISA controller whereas other ISA controllers in the system may be designated as secondary ISA controllers. Each ISA controller in the system is provided with IRQ (interrupt request) enable bits to enable different interrupts for the corresponding ISA bus. Each secondary ISA controller outputs a signal IRQSER as a PCI sideband signal to the primary ISA controller to indicate which IRQs have been asserted on the respective ISA buses. The primary controller receives the IRQSER signal as well as the IRQ signals asserted on its own bus and converts these interrupt requests to PCI bus cycles. The primary bus controller may further provide a bit mask indicating which of a number of direct memory access channels are enabled for the primary bus controller. The primary controller receives direct memory access requests from the second bus system and generates a read or write cycle on the first bus system corresponding to outputs requests enabled by the bit mask.

Claims

1. A multiple bus computer system, comprising:

a first bus system of a first type for interfacing with a central processing unit;

a second bus system of a second type for transmitting data and control signals to and from at least one device;

a primary bus controller, coupled to said first bus system and said second bus system, for controlling the second bus system;

at least one third bus system of the second type, for transmitting data and control signals to and from at least one other device; and

at least one secondary bus controller, coupled to said first bus system and said third bus system, for controlling the at least a third bus system,

wherein said at least one secondary bus controller receives interrupt requests from said at least one third bus system over said first bus system and outputs an interrupt signal on said first bus system to said primary bus controller indicative of interrupt requests generated on said at least one third bus system.

2. A multiple bus computer system, comprising:

a first bus system of a first type for interfacing with a central processing unit;

a second bus system of a second type for transmitting data and control signals to and from at least one device;

a primary bus controller, coupled to said first bus system and said second bus system, for controlling the second bus system;

at least one third bus system of the second type, for transmitting data and control signals to and from at least one other device; and

at least one secondary bus controller, coupled to said first bus system and said third bus system, for controlling the at least a third bus system,

wherein said at least one secondary bus controller receives interrupt requests from said at least one third bus system and outputs an interrupt signal on said first bus system to said primary bus controller indicative of interrupt requests generated on said at least one third bus system, and

wherein said primary bus controller receives said interrupt signal over said first bus system and further receives interrupt requests from said second bus system and outputs a signal on said first bus system indicative of all interrupt requests on said second bus system and said at least one third bus system.

3. The multiple bus computer system of claim 2 wherein said interrupt signal comprises one or more pulses the timed relationship of which indicates the presence of an interrupt request level.

4. The multiple bus computer system of claim 3 wherein said primary bus controller further comprises:

sync pulse generating means, for generating a sync pulse on interrupt signal line on an said first bus system.

5. A multiple bus computer system, comprising:

a first bus system of a first type for interfacing with a central processing unit;

a second bus system of a second type for transmitting data and control signals to and from at least one device;

a primary bus controller, coupled to said first bus system and said second bus system, for controlling the second bus system;

at least one third bus system of the second type, for transmitting data and control signals to and from at least one other device; and

at least one secondary bus controller, coupled to said first bus system and said third bus system, for controlling the at least a third bus system,

wherein said at least one secondary bus controller receives interrupt requests from said at least one third bus system and outputs an interrupt signal on said first bus system to said primary bus controller indicative of interrupt requests generated on said at least one third bus system, and

wherein said at least one secondary bus controller further comprises;

masking means, for providing a bit mask indicating which of a number of interrupt request levels are enabled for said at least one secondary bus controller,

wherein said at least one secondary bus controller receives interrupt requests from said at least one third bus system and generates an interrupt signal on said first bus system for those interrupt levels enabled by said masking means.

6. A multiple bus computer system, comprising:

a first bus system of a first type for interfacing with a central processing unit;

a second bus system of a second type for transmitting data and control signals to and from at least one device;

a primary bus controller, coupled to said first bus system and said second bus system, for controlling the second bus system;

at least one third bus system of the second type, for transmitting data and control signals to and from at least one other device; and

at least one secondary bus controller, coupled to said first bus system and said third bus system, for controlling the at least a third bus system,

wherein said at least one secondary bus controller receives interrupt requests from said at least one third bus system and outputs an interrupt signal on said first bus system to said primary bus controller indicative of interrupt requests generated on said at least one third bus system, and

wherein said primary bus controller further comprises;

masking means, for providing a bit mask indicating which of a number of interrupt request levels are enabled for said primary bus controller,

wherein said primary bus controller receives interrupt requests from said second bus system and combines those interrupt requests enabled by said masking means with interrupt requests received from said interrupt signal to produce a combined interrupt signal representing enabled interrupt requests for all bus systems of the second type in said multiple bus computer system.

7. The multiple bus computer system of claim 6, wherein said primary bus controller further comprises:

means for outputting said combined interrupt signal to said first bus system.

8. The multiple bus computer system of claim 7, wherein said at least one secondary bus controller further comprises:

sync pulse receiving means, for receiving said sync pulse on an interrupt signal line and for generating pulses indicative of interrupt requests on said at least one third system bus in timed relationship to said sync pulse.

9. A multiple bus computer system, comprising:

a first bus system of a first type for interfacing with a central processing unit;

a second bus system of a second type for transmitting data and control signals to and from at least one device;

a primary bus controller, coupled to said first bus system and said second bus system, for controlling the second bus system;

at least one third bus system of the second type, for transmitting data and control signals to and from at least one other device; and

at least one secondary bus controller, coupled to said first bus system and said third bus system, for controlling the at least a third bus system,

wherein said at least one secondary bus controller receives interrupt requests from said at least one third bus system and outputs an interrupt signal on said first bus system to said primary bus controller indicative of interrupt requests generated on said at least one third bus system,

wherein said primary bus controller further comprises masking means, for providing a bit mask indicating which of a number of direct memory access channels are enabled for said primary bus controller, and

wherein said primary controller receives direct memory access requests from said second bus system and generates a read or write cycle on said first bus system corresponding to output requests enabled by said masking means.

10. A multiple bus computer system, comprising:

a first bus system of a first type for interfacing with a central processing unit;

a second bus system of a second type for transmitting data and control signals to and from at least one device;

a primary bus controller, coupled to said first bus system and said second bus system, for controlling the second bus system;

at least one third bus system of the second type, for transmitting data and control signals to and from at least one other device; and

at least one secondary bus controller, coupled to said first bus system and said third bus system, for controlling the at least a third bus system,

wherein said at least one secondary bus controller receives interrupt requests from said at least one third bus system and outputs an interrupt signal on said first bus system to said primary bus controller indicative of interrupt requests generated on said at least one third bus system,

wherein said at least one secondary bus controller further comprises masking means, for providing a bit mask indicating which of a number of direct memory access channels are enabled for said at least one secondary bus controller, and

wherein said at least one secondary bus controller receives direct memory access requests from said at least one third bus system and generates a read or write cycle on said first bus system corresponding to output requests enabled by said masking means.

11. A method of controlling multiple bus systems in a multiple bus computer system including a first bus system of a first type, a second bus system of a second type, a primary bus controller coupled to the first bus system and the second bus system for controlling the second bus system, at least one third bus system of the second type, and at least one secondary bus controller for controlling the at least a third bus system, said method comprising the steps of:

receiving interrupt requests from the at least third bus system over said first bus system in the at least one secondary controller;

generating an interrupt signal on the first bus system indicative of received interrupt requests;

receiving interrupt requests from the second bus system in the primary bus controller;

combining received interrupt requests from the second bus system with the interrupt signal to produce a combined interrupt signal indicative of all interrupt requests for bus systems of the second type; and

outputting the combined interrupt signal to the first bus system.

12. A method of controlling multiple bus systems in a multiple bus computer system including a first bus system of a first type, a second bus system of a second type, a primary bus controller coupled to the first bus system and the second bus system for controlling the second bus system, at least one third bus system of the second type, and at least one secondary bus controller for controlling the at least a third bus system, said method comprising the steps of:

receiving interrupt requests from the at least third bus system in the at least one secondary controller;

generating an interrupt signal on the first bus system indicative of received interrupt requests;

receiving interrupt requests from the second bus system in the primary bus controller;

combining received interrupt requests from the second bus system with the interrupt signal to produce a combined interrupt signal indicative of all interrupt requests for bus systems of the second type;

outputting the combined interrupt signal to the first bus system; and

masking the received interrupt requests in the at least one secondary bus controller with a bit mask indicating enabled interrupt request levels for the at least one third bus system.

13. A method of controlling multiple bus systems in a multiple bus computer system including a first bus system of a first type, a second bus system of a second type, a primary bus controller coupled to the first bus system and the second bus system for controlling the second bus system, at least one third bus system of the second type, and at least one secondary bus controller for controlling the at least a third bus system, said method comprising the steps of:

receiving interrupt requests from the at least third bus system in the at least one secondary controller;

generating an interrupt signal on the first bus system indicative of received interrupt requests;

receiving interrupt requests from the second bus system in the primary bus controller;

combining received interrupt requests from the second bus system with the interrupt signal to produce a combined interrupt signal indicative of all interrupt requests for bus systems of the second type;

outputting the combined interrupt signal to the first bus system; and

masking the received interrupt requests in the primary bus controller with a bit mask indicating enabled interrupt request levels for the second bus system.

14. A method of controlling multiple bus systems in a multiple bus computer system including a first bus system of a first type, a second bus system of a second type, a primary bus controller coupled to the first bus system and the second bus system for controlling the second bus system, at least one third bus system of the second type, and at least one secondary bus controller for controlling the at least a third bus system, said method comprising the steps of:

receiving interrupt requests from the at least third bus system in the at least one secondary controller;

generating an interrupt signal on the first bus system indicative of received interrupt requests;

receiving interrupt requests from the second bus system in the primary bus controller;

combining received interrupt requests from the second bus system with the interrupt signal to produce a combined interrupt signal indicative of all interrupt requests for bus systems of the second type; and

outputting the combined interrupt signal to the first bus system,

wherein said step of generating an interrupt signal on the first bus system comprises the steps of;

generating, with the primary controller, a sync pulse on an interrupt request line on the first bus system;

receiving the sync pulse in at least one of the at least one secondary controllers; and

generating, in response to an interrupt request generated on at least one of the at least one third bus systems, at least one interrupt pulse on the interrupt request line, the at least one interrupt pulse having a timed relationship to the sync pulse indicating a level of the at least one interrupt request generated on the at least one of the at least one third bus.

15. A method of controlling multiple bus systems in a multiple bus computer system including a first bus system of a first type, a second bus system of a second type, a primary bus controller coupled to the first bus system and the second bus system for controlling the second bus system, at least one third bus system of the second type, and at least one secondary bus controller for controlling the at least a third bus system, said method comprising the steps of:

receiving interrupt requests from the at least third bus system in the at least one secondary controller;

generating an interrupt signal on the first bus system indicative of received interrupt requests;

receiving interrupt requests from the second bus system in the primary bus controller;

combining received interrupt requests from the second bus system with the interrupt signal to produce a combined interrupt signal indicative of all interrupt requests for bus systems of the second type;

outputting the combined interrupt signal to the first bus system;

providing a bit mask in the primary bus controller indicating which of a number of direct memory access channels are enabled for the primary bus controller;

receiving direct memory access requests from the second bus system; and

generating a read or write cycle on the first bus system corresponding to output requests enabled by the bit mask.

16. A method of controlling multiple bus systems in a multiple bus computer system including a first bus system of a first type, a second bus system of a second type, a primary bus controller coupled to the first bus system and the second bus system for controlling the second bus system, at least one third bus system of the second type, and at least one secondary bus controller for controlling the at least a third bus system, said method comprising the steps of:

receiving interrupt requests from the at least third bus system in the at least one secondary controller;

generating an interrupt signal on the first bus system indicative of received interrupt requests;

receiving interrupt requests from the second bus system in the primary bus controller;

combining received interrupt requests from the second bus system with the interrupt signal to produce a combined interrupt signal indicative of all interrupt requests for bus systems of the second type;

outputting the combined interrupt signal to the first bus system;

providing a bit mask indicating which of a number of direct memory access channels are enabled for said at least one secondary bus controller;

receiving direct memory access requests from the at least one third bus system; and

generating a read or write cycle on the first bus system corresponding to output requests enabled by the masking means.

17. A multiple bus computer system, comprising:

a first bus system of a first type for interfacing with a central processing unit;

a second bus system of a second type for transmitting data and control signals to and from at least one device;

a primary bus controller, coupled to said first bus system and said second bus system, for controlling the second bus system, said primary bus controller including an interrupt controller;

at least one third bus system of the second type, for transmitting data and control signals to and from at least one other device; and

at least one secondary bus controller, coupled to said first bus system and said third bus system, for controlling the at least a third bus system,

wherein said at least one secondary bus controller receives interrupt requests from said at least one third bus system and outputs the interrupt requests to said primary bus controller indicative of interrupt requests generated on said at least one third bus system.

18. A method of controlling multiple bus systems in a multiple bus computer system including a first bus system of a first type, a second bus system of a second type, a primary bus controller coupled to the first bus system and the second bus system for controlling the second bus system, the primary bus controller including an interrupt controller, at least one third bus system of the second type, and at least one secondary bus controller for controlling the at least a third bus system, said method comprising the steps of:

receiving interrupt requests from the at least third bus system in the at least one secondary controller;

transmitting the interrupt requests from the at least third bus system to the primary bus controller;

receiving interrupt requests from the second bus system in the primary bus controller;

combining received interrupt requests from the second bus system with interrupt requests from the at least third bus system to produce a combined interrupt signal indicative of all interrupt requests for bus systems of the second type; and

outputting the combined interrupt signal to the first bus system.