Method of making a trench MOSFET with multi-resistivity drain to provide low on-resistance by varying dopant concentration in epitaxial layer

• US 5,674,766 A
• Filed: 04/26/1995
• Issued: 10/07/1997
• Est. Priority Date: 12/30/1994
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Williams, Richard K., Darwish, Mohamed N.
• Primary Examiner(s): Bowers, Jr., Charles L.
• Assistant Examiner(s): GURLEY, LYNNE ANN
• Application Number:
  US08/429,414
• Time in Patent Office: 895 Days
• Field of Search: 437/40 RG, 437/40 DM, 437/41 DM, 437/81, 437/108, 437/110, 437/112, 437/DIG. 971, 437/DIG. 973, 257/329, 257/330, 257/331, 257/332, 257/341, 257/408
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A MOSFET switch with a gate formed in a trench has a drain which includes a region of relatively high resistivity adjacent the trench and a region of relatively low resistivity further away from the trench. The drain may also include a "delta" layer having even lower resistivity in a central region of the MOSFET cell. The high resistivity region limits the strength of the electric field at the edge of the trench (particularly where there are any sharp corners) and thereby avoids damage to the gate oxide layer. The central "delta" layer helps to insure that any breakdown will occur near the center of the MOSFET cell, away from the gate oxide, and to lower the resistance of the MOSFET when it is in an on condition.

Claims

1. A method of fabricating a MOSFET in a semiconductor material, said method comprising the steps of:

providing a substrate;

growing an epitaxial layer;

introducing a dopant of a first conductivity type into said epitaxial layer while said epitaxial layer is being grown;

reducing the concentration of said dopant of said first conductivity type being introduced into said epitaxial layer while said epitaxial layer is being grown so as to form a region of high resistivity, said region of high resistivity having a resistivity which is higher than a resistivity of other portions of said epitaxial layer;

etching a trench in said semiconductor material;

forming an insulated gate in said trench;

introducing a dopant of a second conductivity type into said semiconductor material so as to form a body region; and

introducing a dopant of said first conductivity type into said semiconductor material so as to form a source region.

2. The method of claim 1 wherein said step of reducing the concentration of said dopant of said first conductivity type includes reducing the concentration of said dopant of said first conductivity type abruptly from a first concentration to a second concentration.

3. The method of claim 1 wherein said step of reducing the concentration of said dopant of said first conductivity type includes reducing the concentration of said dopant of said first conductivity type gradually and monotonically.

4. The method of claim 1 wherein said step of etching said trench precedes said step of introducing said dopant of said second conductivity type to form said body region.

5. The method of claim 1 wherein said step of etching said trench follows said step of introducing said dopant of said second conductivity type to form said body region.

6. The method of claim 1 wherein said step of etching said trench includes etching said trench so as to form a MOSFET cell.

7. The method of claim 6 wherein said MOSFET cell is formed between parallel trench stripes.

8. The method of claim 6 wherein said MOSFET cell is formed in a polygonal shape.

9. The method of claim 6 further comprising the step of introducing said dopant of said second conductivity type near a center of said MOSFET cell so as to form a central diffusion.

10. The method of claim 9 wherein said central diffusion extends to a level below a bottom of said trench.

11. The method of claim 1 further comprising the step of introducing a dopant of said first conductivity type so as to form a delta layer disposed laterally from said trench, said delta layer having a concentration of said dopant of said first conductivity type greater than a concentration of said dopant of said first conductivity type in said region of high resistivity.

12. The method of claim 11 wherein said delta layer is formed by introducing said dopant of said first conductivity type during the step of growing said epitaxial layer.

13. The method of claim 11 wherein said delta layer is formed by implanting said dopant of said first conductivity type into said semiconductor material.

14. The method of claim 13 wherein said delta layer extends laterally to a side wall of said trench.

15. The method of claim 13 further comprising the step of forming a mask before the introduction of said dopant of said first conductivity type to form said delta layer such that said delta layer does not extend to a side wall of said trench.

16. The method of claim 15 wherein said mask is also used to open a contact region at a surface of said semiconductor material.

17. The method of claim 15 wherein said step of reducing the concentration of said dopant of said first conductivity type includes reducing the concentration of said dopant of said first conductivity type abruptly from a first concentration to a second concentration.

18. The method of claim 15 wherein said step of etching said trench includes etching said trench so as to form a MOSFET cell.

19. The method of claim 18 further comprising the step of introducing said dopant of said second conductivity type near a center of said MOSFET cell so as to form a central diffusion.

20. The method of claim 19 wherein said central diffusion is formed through said mask.

21. The method of claim 20 wherein said mask is also used to open a contact region at a surface of said semiconductor material.