Method of producing a single piece package for semiconductor die

• US 5,674,785 A
• Filed: 11/27/1995
• Issued: 10/07/1997
• Est. Priority Date: 11/27/1995
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Farnworth, Warren M., Wood, Alan G., Akram, Salman
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): Turner, Kevin F.
• Application Number:
  US08/563,191
• Time in Patent Office: 680 Days
• Field of Search: 437/209, 437/215, 437/217, 437/915
• US Class Current: 438/15
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/06135 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/06136 Covering only the central area of the surface to be connected, i.e. central arrangements
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/1624 the bump connector connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49883 the conductive materials containing organic materials or pastes, e.g. for thick films for printed circuits H05K1/092
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18165 : of a wire bonded chip
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49133 : with component orienting

Abstract

A method for packaging a bare semiconductor die using a one piece package body with a pattern of external conductors is provided. The package body includes a die mounting location and an interconnect opening that aligns with the bond pads on the die. Electrical interconnects, such as wire bonds, are formed through the interconnect opening to establish electrical communication between the bond pads on the die and the conductors on the package body. The conductors on the package body can include solder bumps to permit the package to be flip chip mounted to a supporting substrate such as a printed circuit board or to be mounted in a chip-on-board configuration. The package can be fabricated by bulk micro-machining silicon wafers to form the package bodies, attaching the dice to the package bodies, and then singulating the wafer. Alternately the package body can be formed of a FR-4 material. In addition, multiple dice can be attached to a package body to form a multi-chip module.

Claims

1. A method for packaging a semiconductor die comprising:

forming a package body with a die mounting location;

forming an interconnect opening through the package body, said opening extending from the die mounting location to a surface of the package body;

forming a pattern of grooves on the surface;

forming an insulating layer in the opening and on the surface;

forming pattern of conductors within the grooves;

mounting the die circuit side down on the die mounting location with a pattern of bond pads on the die accessible through the interconnect opening; and

forming an electrical interconnection between the pattern of bond pads and the pattern of conductors by wire bonding through the interconnect opening.

2. The method as claimed in claim 1 further comprising forming the package body and interconnect opening in a configuration for packaging the die or for packaging a second die having a different pattern of bond pads.

3. The method as claimed in claim 1 further comprising forming a second interconnect opening through the package body and wire bonding through the second interconnect opening to a second pattern of bond pads on the die.

4. The method as claimed in claim 1 further comprising forming a capture groove in the surface and forming a metal bump on the capture groove in electrical communication with a selected conductor.

5. The method as claimed in claim 1 further comprising forming a wire bonding shelf on the surface for wire bonding to the pattern of conductors.

6. The method as claimed in claim 1 wherein the package body comprises silicon.

7. The method as claimed in claim 1 further comprising forming a pattern of bumps on the pattern of conductors, said bumps configured for flip chip mounting the package to a substrate.

8. The method as claimed in claim 1 further comprising aligning the bond pads on the die with the interconnect opening using optical alignment.

9. The method as claimed in claim 1 further comprising aligning the bond pads on the die with the interconnect opening using an alignment fixture.

10. The method as claimed in claim 1 further comprising flip chip mounting the package body to a supporting substrate with the pattern of conductors in electrical contact with a pattern of contact locations on the supporting substrate.

11. The method as claimed in claim 1 further comprising mounting the package body on a supporting substrate in a chip on board configuration with the pattern of conductors wire bonded to a pattern of contact locations on the supporting substrate.

12. The method as claimed in claim 1 wherein forming the package body comprises etching a die cavity and then etching the interconnect opening.

13. The method as claimed in claim 1 wherein forming the pattern of conductors comprises forming a layer of polyimide on the conductors.

14. The method as claimed in claim 1 wherein forming the pattern of conductors comprises a screen printing process.

15. The method as claimed in claim 1 further comprising encapsulating the die on the die mounting location by depositing and curing a material on the die and package body.

16. The method as claimed in claim 1 further comprising depositing and curing a material over the interconnect opening and a wire bonding area.

17. The method as claimed in claim 1 further comprising mounting the package on a supporting substrate in a chip on board configuration with the pattern of conductors wire bonded to a pattern of contact locations on the supporting substrate and then encapsulating the package using a curable material.

18. A method for packaging a semiconductor die comprising:

providing a substrate;

providing the die with a pattern of bond pads having solder bumps formed thereon;

forming a die mounting location on the substrate to form a package body;

forming an opening from the die mounting location to a surface of the package body;

forming a pattern of grooves on the surface of the package body;

forming a pattern of conductors within the grooves;

aligning the bond pads on the die with the opening in the package body;

placing the die circuit side down on the die mounting location; and

electrically connecting the bond pads on the die to the conductors on the package body by reflowing the solder bumps through the opening onto the conductors.

19. The method as claimed in claim 18 further comprising forming an insulating layer on the surface and opening prior to forming the pattern of conductors.

20. The method as claimed in claim 18 further comprising forming the package body and interconnect opening in a configuration for packaging the die or for packaging a second die having a different pattern of bond pads.

21. The method as claimed in claim 18 wherein the substrate comprises silicon.

22. The method as claimed in claim 18 further comprising forming the pattern of conductors by a process selected from the group consisting of metallization, screen printing and sputtering.

23. The method as claimed in claim 18 further comprising forming a pattern of metal bumps on the pattern of conductors for mounting the package in electrical contact with contact locations on a supporting substrate.

24. The method as claimed in claim 18 further comprising encapsulating the die on the die mounting location by depositing and curing a material.

25. The method as claimed in claim 18 further comprising mounting and electrically interconnecting a plurality of dice to the package body.

26. The method as claimed in claim 25 wherein the dice and package body comprise a multi-chip-module.

27. The method as claimed in claim 18 further comprising testing the die following packaging using the package body.

28. A method for packaging semiconductor dice comprising:

providing a silicon wafer;

forming a plurality of packages by etching a plurality of die mounting locations into the wafer, etching a plurality of through openings from a surface of the wafer to the die mounting locations, forming an insulating layer on the surface and sidewalls of the openings, forming a plurality of patterns of conductors on the surface, forming a plurality of grooves on the surface, and forming a plurality of patterns of solder balls within the plurality of grooves in electrical communication with the patterns of conductors;

placing the dice circuit side down on the die mounting locations;

singulating the packages from the wafer; and

electrically connecting bond pads on the dice to the conductors on the packages by wire bonding or solder reflowing through the openings.

29. The method as claimed in claim 28 wherein etching the die mounting locations and openings comprises wet etching with an etchant solution.

30. The method as claimed in claim 28 further comprising forming the packages and openings in a configuration for packaging the dice or for packaging different dice having different patterns of bond pads.

31. The method as claimed in claim 28 wherein forming the conductors comprises a process selected from the group consisting of metallization, screen printing and sputtering.

32. The method as claimed in claim 28 further comprising forming a second pattern of grooves in the surface for and forming the pattern of conductors within the second pattern of grooves.

33. The method as claimed in claim 28 wherein the pattern of grooves is formed such that a groove is proximate to a selected edge of each package.

34. The method as claimed in claim 28 further comprising forming wire bonding shelves in the surface for the conductors.

35. The method as claimed in claim 28 further comprising flip chip mounting at least one package to a supporting substrate.

36. A method for packaging a semiconductor die having a pattern of bond pads comprising:

forming a single piece package body with a die mounting location;

forming an interconnect opening through the package body, said opening extending from the die mounting location to a surface of the package body;

forming a pattern of conductors on the surface;

forming a groove on the surface;

forming metal bumps on the groove in electrical communication with the pattern of conductors;

mounting the die circuit side down on the die mounting location with the pattern of bond pads on the die accessible through the interconnect opening; and

forming an electrical interconnection through the interconnect opening to the pattern of bond pads on the die and the pattern of conductors on the package body.

37. The method as claimed in claim 36 wherein forming the electrical interconnection comprises wire bonding.

38. The method as claimed in claims 36 wherein forming the electrical interconnection comprises reflowing solder bumps formed on the pattern of bond pads.

39. The method as claimed in claim 36 wherein the package body comprises silicon.

40. The method as claimed in claim 36 wherein the package body comprises an electrically insulating glass filled resin.

41. The method as claimed in claim 36 wherein a plurality of dice are mounted to the die mounting location in electrical communication with the pattern of conductors.