Semiconductor structure incorporating thin film transistors with undoped cap oxide layers

• US 5,675,185 A
• Filed: 09/29/1995
• Issued: 10/07/1997
• Est. Priority Date: 09/29/1995
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Nowak, Edward Joseph, White, Francis Roger, Mann, Randy William, Chen, Bomy Able, Kulkarni, Subhash Balakrishna, Rausch, Werner Alois, Lasky, Jerome Bret
• Primary Examiner(s): WHITEHEAD JR, CARL W
• Application Number:
  US08/537,219
• Time in Patent Office: 739 Days
• Field of Search: 257/750, 257/734, 257/637, 257/751, 257/752, 257/754, 257/774, 257/758, 257/759
• US Class Current: 257/774
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]

Abstract

An improved field effect transistor (FET) structure is disclosed. It comprises a first insulator layer containing at least one primary level stud extending through the layer; an undoped cap oxide layer disposed over the insulator layer and abutting the upper region of each stud; a primary level thin film transistor (TFT) disposed over the undoped cap oxide layer; and a planarized oxide layer disposed over the TFT. Multiple TFT'"'"'s can be stacked vertically, and connected to other levels of studs and metal interconnection layers. Another embodiment of the invention includes the use of a protective interfacial cap over the surface of tungsten-type studs. The FET structure can serve as a component of a static random access memory (SRAM) cell. Related processes are also disclosed.

Claims

1. A field effect transistor (FET) structure, comprising:

a) a first insulator layer containing at least one primary level stud extending through the layer;

b) an undoped cap oxide layer disposed over the insulator layer, and abutting the upper region of each stud;

c) a primary level thin film transistor (TFT) disposed over the undoped cap oxide layer; and

d) a planarized dielectric layer disposed over the thin film transistor.

2. The structure of claim 1, wherein the primary level TFT comprises:

c1) doped polysilicon source and drain regions disposed over a portion of the cap oxide layer and over the exposed upper surface of the metallic stud, wherein the source and drain regions are separated from each other by a channel;

c2) a gate dielectric layer disposed over the channel, source, and drain regions; and

c3) a transistor gate electrode disposed over a portion of the gate dielectric layer, and substantially self-aligned with the channel.

3. The structure of claim 1, wherein the first insulator layer comprises an oxide, a nitride, or glass material.

4. The structure of claim 1, wherein the metallic stud comprises tungsten, or an alloy of tungsten.

5. The structure of claim 1, wherein the dielectric layer of component (d) comprises CVD oxide.

6. The structure of claim 2, wherein the source and drain regions are formed from an amorphous polysilicon layer.

7. The structure of claim 2, wherein the source and drain regions exhibit P+ conductivity.

8. The structure of claim 1, wherein the lower terminus of the stud is connected to an active electrical device.

9. The structure of claim 1, wherein the lower terminus of the stud is embedded in an insulator material.

10. The structure of claim 1, wherein at least one secondary level stud is attached at its lower terminus to an upper surface of a primary level stud.

11. The structure of claim 10, wherein attachment between the primary level stud and the secondary level stud is made by a bonding layer which comprises titanium.

12. The structure of claim 2, wherein at least one secondary level stud is attached at its lower terminus to at least one of the polysilicon source or drain regions of component (c1).

13. The structure of claim 12, wherein the secondary level stud is attached at its upper terminus to a first metal interconnection layer.

14. The structure of claim 13, comprising a plurality of additional metal interconnection layers, substantially parallel to and vertically disposed over the first metal interconnection layer, and separated from each other by additional insulator layers.

15. The structure of claim 14, wherein the secondary level stud is attached at its upper terminus to a source or drain region of a secondary-level thin film transistor.

16. The structure of claim 15, wherein a tertiary level stud is attached at its lower terminus to a source or drain region of the secondary level thin film transistor, and is attached at its upper terminus to either a metal interconnection layer or to the source or drain region of a tertiary level thin film transistor.

17. The structure of claim 1, wherein the studs are substantially cylindrical in shape, and have diameters in the range of about 0.4 micron to about 0.8 micron.

18. The structure of claim 2, wherein a protective, interfacial layer of doped polysilicon is disposed between the lower surface of the source and drain regions and the upper surface of the primary level stud, covering the surface of the stud.

19. A field effect transistor (FET) structure, comprising:

a) a first insulator layer containing at least one primary level stud extending through the layer;

b) an undoped cap oxide layer disposed over the insulator layer, and abutting the upper region of each stud;

c) a primary level thin film transistor (TFT) disposed over the undoped cap oxide layer, said TFT itself comprising;

c1) doped polysilicon source and drain regions disposed over a portion of the cap oxide layer and over the exposed upper surface of the stud, wherein the source and drain regions are separated from each other by a channel;

c2) a second insulator layer disposed over the channel, source, and drain regions; and

c3) a transistor gate electrode disposed over a portion of the second insulator layer, and substantially self-aligned with the channel,

wherein a protective, interfacial layer of doped polysilicon is disposed between the lower surface of the source and drain regions and the upper surface of the primary level stud, covering the surface of the stud; and

d) a planarized dielectric layer disposed over the TFT.

20. The structure of claim 19, wherein at least one secondary level stud is attached at its lower terminus to at least one of the polysilicon source or drain regions of component (c1).

21. The structure of claim 20, wherein the secondary level stud is attached at its upper terminus to a first metal interconnection layer.

22. The structure of claim 21, comprising a plurality of additional metal interconnection layers, substantially parallel to and vertically disposed over the first metal interconnection layer, and separated from each other by additional insulator layers.

23. The structure of claim 22, wherein the secondary level stud is attached at its upper terminus to a source or drain region of a secondary-level thin film transistor.

24. The structure of claim 23, wherein a tertiary level stud is attached at its lower terminus to a source or drain region of the secondary level thin film transistor, and is attached at its upper terminus to either a metal interconnection layer or to the source or drain region of a tertiary level thin film transistor.