Thin film resistors on organic surfaces

• US 5,675,310 A
• Filed: 12/05/1994
• Issued: 10/07/1997
• Est. Priority Date: 12/05/1994
• Status: Expired due to Term

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Rose, James Wilson, Wojnarowski, Robert John, Paik, Kyung Wook, Gdula, Michael
• Primary Examiner(s): Walberg, Teresa J.
• Assistant Examiner(s): Valencia, Ralphael
• Application Number:
  US08/349,228
• Time in Patent Office: 1,037 Days
• Field of Search: 338/22 R, 338/22 SD, 338/307-309, 338/312, 437/60, 437/918, 148/DIG. 136, 29/621
• US Class Current: 338/309
• CPC Class Codes: H01C 1/032 plural layers surrounding the resistive element H01C1/028 takes precedence
• CPC Class Codes: H01C 17/075 by thin film techniques H01C17/20 takes precedence
• CPC Class Codes: H01C 7/006 Thin film resistors
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/82039 using a laser
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 2924/01077 Iridium [Ir]
• CPC Class Codes: H05K 1/0268 for electrical inspection or testing
• CPC Class Codes: H05K 1/167 incorporating printed resistors
• CPC Class Codes: H05K 2201/0317 Thin film conductor layer; Thin film passive component
• CPC Class Codes: H05K 2203/0361 Stripping a part of an upper metal layer to expose a lower metal layer, e.g. by etching or using a laser
• CPC Class Codes: H05K 2203/171 Tuning, e.g. by trimming of printed components or high frequency circuits
• CPC Class Codes: H05K 3/388 by the use of a metallic or inorganic thin film adhesion layer
• CPC Class Codes: Y10S 148/136 Resistors
• CPC Class Codes: Y10T 29/49101 Applying terminal

Abstract

A method for fabricating a thin film resistor comprises applying a tantalum nitride layer over a dielectric layer, applying a metallization layer over the tantalum nitride layer, and patterning the metallization layer with a first portion of the metallization layer situated apart from a second portion of the metallization layer and both the first and second portions being at least partially situated on the tantalum nitride layer. In one embodiment, after patterning the metallization layer, the resistance value between the first and second portions of the metallization layer is determined and compared to a predetermined resistance value, and at least one of the first and second portions is trimmed to obtain a modified resistance value between the first and second portions that is closer to the predetermined resistance value than the determined resistance value.

Claims

1. A thin film resistor, comprising:

an organic dielectric layer;

a tantalum nitride layer deposited over the dielectric layer;

a patterned metallization layer over the tantalum nitride layer, a first portion of the metallization layer situated apart from a second portion of the metallization layer with both the first and second portions being at least partially situated on the tantalum nitride layer;

wherein the dielectric layer is situated over a substrate having a chip well with a circuit chip having chip pads situated in the chip well, the dielectric layer having vias to the chip pads, and the tantalum nitride layer and the metallization layer extend into selected ones of the vias.

2. The thin film resistor of claim 1, wherein the tantalum nitride layer comprises a hexagonal closed packed structure.

3. The thin film resistor of claim 2, wherein the dielectric layer comprises a polyimide.

4. The thin film resistor of claim 3, wherein the polyimide includes filler material.

5. The thin film resistor of claim 4, wherein the filler material is one selected from the group consisting of stone and mineral.

6. The thin film resistor of claim 1, further including:

an additional dielectric layer over the metallization layer;

an additional tantalum nitride layer over the additional dielectric layer;

a patterned additional metallization layer (over the additional tantalum nitride layer, a first additional portion of the additional metallization layer situated apart from a second additional portion of the additional metallization layer with both the first and second additional portions being at least partially situated on the additional tantalum nitride layer.

7. A method for fabricating a thin film resistor, comprising the steps of:

applying a dielectric layer over a substrate having a chip well with an integrated circuit chip having chip pads situated in the chip well;

forming vias through the dielectric layer to the chip pads;

applying a tantalum nitride layer over an organic dielectric layer and in selected ones of the vias;

depositing a metallization layer over the tantalum nitride layer and in the selected ones of the vias; and

patterning the metallization layer with a first portion of the metallization layer situated apart from a second portion of the metallization layer and both the first and second portions being at least partially situated on the tantalum nitride layer.

8. A circuit module, comprising:

a substrate having a chip well with a circuit chip having chip pads situated in the chip well;

an organic dielectric layer over the substrate and circuit chip, the dielectric layer having vias to the chip pads;

a tantalum nitride layer over the dielectric layer, the tantalum nitride layer comprising a hexagonal closed packed structure and extending into selected ones of the vias; and

a patterned metallization layer over the tantalum nitride layer, a first portion of the metallization layer situated apart from a second portion of the metallization layer with both the first and second portions being at least partially situated on the tantalum nitride layer, the metallization layer extending into the selected ones of the vias.

9. The circuit module of claim 8, further including

an additional dielectric layer over the metallization layer;

an additional tantalum nitride layer over the additional dielectric layer, the additional tantalum nitride layer and the additional dielectric layer having at least one additional via extending to the metallization layer;

a patterned additional metallization layer over the additional tantalum nitride layer and extending into the at least one additional via, a first additional portion of the additional metallization layer situated apart from a second additional portion of the additional metallization layer with both the first and second additional portions being at least partially situated on the additional tantalum nitride layer.