Analog memory unit

• US 5,675,336 A
• Filed: 02/15/1996
• Issued: 10/07/1997
• Est. Priority Date: 02/15/1996
• Status: Expired due to Fees

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Hakkarainen, Juka Mikko
• Primary Examiner(s): DeBoer, Todd
• Application Number:
  US08/601,409
• Time in Patent Office: 600 Days
• Field of Search: 341/110, 341/135, 341/144, 341/145, 341/146, 341/147, 341/148, 341/153, 341/154, 361/93, 327/352, 327/361
• US Class Current: 341/135
• CPC Class Codes: G11C 7/16 Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters

Abstract

An analog memory unit that can be implemented, at least in part, on an application specific integrated circuit (ASIC), utilizes at least the ASIC arithmetic logic unit (ALU) to enhance performance and to generate and store an accurate measure of power line thermal status. The memory unit includes an analog-to-digital (A/D) converter for converting an input analog signal from a parallel R-C circuit to a digital signal and a scaler for scaling the digital signal from the A/D converter to within a range acceptable for further processing. The memory unit also includes an arithmetic logic unit (ALU) which receives input signals from the scaler and from a digital thermal memory. The input signal supplied to the ALU from the digital thermal memory is a four bit (digital) value proportional to the measured actual thermal status of the subject power line. The output of the ALU is connected to the input of latches which latch, or store, the digital signal produced by the ALU. The ALU output signal is representative of the difference between charge on the R-C circuit and the most recently measured actual thermal status of the power line. The latches are connected to a digital-to-analog converter which has its output connected to the input of the A/D converter and to the R-C circuit.

Claims

1. An analog memory unit comprising:

a parallel resistor-capacitor circuit comprising a resistor and a capacitor electrically connected in parallel;

an analog-to-digital (A/D) converter coupled to said parallel resistor-capacitor circuit for converting an analog output signal from said parallel resistor-capacitor circuit to a digital signal;

a scaler coupled to an output of said analog-to-digital converter for scaling a digital signal produced by said analog-to-digital converter;

a memory module having a digital value stored therein;

an arithmetic logic unit coupled to receive input signals from said scaler and from said memory module;

a plurality of latches coupled to an output of said arithmetic logic unit for accumulating digital output signal from said arithmetic logic unit; and

a digital-to-analog converter having its output coupled to an input of said analog-to-digital converter and to said parallel resistor-capacitor circuit.

2. The analog memory unit of claim 1 wherein said scaler, said memory module and said arithmetic logic unit each have a resolution of four (4) bits.

3. The analog memory unit of claim 1 wherein said arithmetic logic unit is adapted to compare a scaled output signal from said scaler with said digital value stored in said memory module, and to produce a digital difference signal representative of a difference between the scaled signal and the stored digital value.

4. The analog memory unit of claim 1 wherein said analog-to-digital converter, said scaler, said memory module, said arithmetic logic unit, said latches, and said digital-m-analog converter are implemented on an application specific integrated circuit.

5. The analog memory unit of claim 4 wherein said parallel resistor-capacitor circuit is implemented on said application specific integrated circuit.

6. The analog memory unit of claim 1 wherein said digital-to-analog converter comprises a plurality of control field effect transistors and a current mirror, each of said control field effect transistors being electrically coupled to a respective branch of said current mirror, each of said branches being adapted to generate a current equal to a multiple of a base current.

7. The analog memory unit of claim 6 wherein each of said control field effect transistors is electrically coupled to a respective one of said plurality of latches.

8. The analog memory unit of claim 7 wherein an output signal Iout of said analog-to-digital converter is equal to:

space="preserve" listing-type="equation">Iout=(B0×

I)+(B1×

2I)+(B2×

4I)+(B3×

8I),

where bits B0, B1, B2 and B3 represent digital value in one of said respective latches of said plurality of latches associated with said each of said control field effect transistors.

9. The analog memory unit of claim 6 wherein said analog-to-digital converter comprises an eight bit converter.

10. The analog memory unit of claim 9 wherein, when energized, said current mirror carries lgA of current in a first branch thereof, 2 μ

A in a second branch thereof, 4 μ

A in a third branch thereof, 8 μ

A in a fourth branch thereof, 16 μ

A in a fifth branch thereof, 32 μ

A in a sixth branch thereof, 64 μ

A in a seventh branch thereof, and 128 μ

A in an eighth branch thereof.

11. The analog memory unit of claim 10 wherein a maximum output signal from said digital-D-analog converter is 255 μ

A.

12. An analog memory unit comprising:

a parallel resistor-capacitor circuit comprising a resistor and a capacitor electdcal/y connected in parallel; and

an application specific integrated circuit comprising;

an analog-to-digital (A/D) converter coupled to said parallel resistor-capacitor circuit for converting an analog output signal from said parallel resistor-capacitor circuit to a digital signal;

an arithmetic logic unit coupled to receive a signal representative of the digital output signal from said anaiog-to-digital converter;

a plurality of latches coupled to an output of said arithmetic logic unit for accumulating digital output signals from said arithmetic logic unit; and

a digital-to-analog converter having its output coupled to an input of said analog-to-digital converter and to said parallel resistor-capacitor circuit.

13. The analog memory unit of claim 12 wherein said application specific integrated circuit further comprises:

a memory module having a digital value stored therein, said memory module being coupled to provide output signals to said arithmetic logic unit.

14. The analog memory unit of claim 13 wherein said arithmetic logic unit includes a scaler coupled to an output of said analog-to-digital converter for scaling a digital signal produced by said analog-to-digital converter.

15. The analog memory unit of claim 14 wherein said arithmetic logic unit compares a scaled digital output signal from said analog-to-digital converter with said digital value stored in said memory module, and said arithmetic logic unit produces a digital difference signal representative of a difference between the scaled signal and the stored digital value.

16. The analog memory unit of claim 13 wherein said digital-to-analog converter comprises a plurality of control field effect transistors, each of said control field effect transistors being electrically coupled to a respective branch of a current mirror, each of said branches being adapted to generate a current equal to a multiple of a base current.

17. The analog memory unit of claim 16 wherein each of said control field effect transistors is electrically coupled to a respective one of said plurality of latches.