Charge-redistribution analog-to-digital converter with reduced comparator-hysteresis effects
First Claim
1. A successive-approximation analog-to-digital converter (ADC) circuit comprising:
- a comparator having a first input coupled to an analog input signal that is to be converted into an ADC-digital-output value by the ADC circuit, said ADC-digital-output value having a plurality of N bits, a second input, and an output;
a coarse ADC converter having an input coupled to said analog input signal, and an M-bit coarse digital output, wherein said coarse ADC converter generates a plurality of M bits corresponding to M most-significant bits of said ADC-digital-output value on said M-bit coarse digital output, and wherein M is less than N;
successive-approximation logic having a first input connected to said output of said comparator, a second input connected to said M-bit coarse digital output, and an output; and
a digital-to-analog converter having an input connected to said output of said successive-approximation logic and an analog output coupled to said second input of said comparator.
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Abstract
Methods and apparatus for an analog-to-digital converter (ADC) with reduced comparator-hysteresis effects. One embodiment uses a charge-redistribution ADC. One method performs an initial coarse analog-to-digital conversion to avoid overdriving an analog voltage comparator. One such method includes a redundant capacitor in an array of charge-redistribution capacitors used in the ADC for sample-and-hold and successive-approximation functions. Another method performs a traditional initial successive-approximation analog-to-digital conversion, and then performs an additional conversion-step test based on the least-significant bit of the initial result to correct for comparator errors in the initial conversion.
97 Citations
42 Claims
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1. A successive-approximation analog-to-digital converter (ADC) circuit comprising:
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a comparator having a first input coupled to an analog input signal that is to be converted into an ADC-digital-output value by the ADC circuit, said ADC-digital-output value having a plurality of N bits, a second input, and an output; a coarse ADC converter having an input coupled to said analog input signal, and an M-bit coarse digital output, wherein said coarse ADC converter generates a plurality of M bits corresponding to M most-significant bits of said ADC-digital-output value on said M-bit coarse digital output, and wherein M is less than N; successive-approximation logic having a first input connected to said output of said comparator, a second input connected to said M-bit coarse digital output, and an output; and a digital-to-analog converter having an input connected to said output of said successive-approximation logic and an analog output coupled to said second input of said comparator. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A successive-approximation analog-to-digital converter (ADC) circuit for reducing comparator-hysteresis effects while converting an input analog signal into an ADC-digital-output value, said ADC-digital-output value having a plurality of N bits, said circuit comprising:
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a comparator having a first input, a second input, and an output; a coarse ADC converter having an input coupled to said input analog signs, and an M-bit coarse digital output, wherein said coarse ADC converter generates a plurality of M bits corresponding to M most-significant bits of said ADC-digital-output value on said M-bit coarse digital output, and wherein M is less than N; successive-approximation logic having a first input connected to said output of said comparator, a second input connected to said M-bit coarse digital output, and an output; and a digital-to-analog converter having an input connected to said output of said successive-approximation logic and an analog output coupled to said second input of said comparator; wherein said digital-to-analog converter comprises a charge-redistribution converter coupled to said input analog signal, said charge-redistribution converter comprising a capacitor array, said capacitor array comprising a capacitor corresponding to each bit in the output digital value. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A method for reducing comparator-hysteresis effects while performing successive-approximation analog-to-digital conversion of an input analog signal into an output digital value, said output digital value having a plurality of N bits, said method comprising the steps of:
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(a) performing a coarse analog-to-digital conversion to generate a plurality of M bits corresponding to M most-significant bits of said output digital value, wherein M is less than N, wherein the step of performing a coarse analog-to-digital conversion includes the substantially simultaneous step of sampling said input analog signal to obtain a sampled analog signal; (b) coupling said M bits to an internal digital approximation value; (c) converting said internal digital approximation value to a corresponding internal analog signal; (d) comparing said internal analog signal to said sampled analog signal to obtain a test result; (e) generating a next-most-significant bit of said internal digital approximation value as a function of said test result; (f) successively approximating said output digital value by iteratively repeating steps (c), (d), and (e). - View Dependent Claims (17, 18, 19, 20, 21, 22)
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23. A method for reducing comparator-hysteresis effects while performing successive-approximation analog-to-digital conversion of an input analog signal into an output digital value, said output digital value having a plurality of N bits, said method comprising the steps of:
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(a) generating an initial internal digital approximation value; (b0) if a least-significant bit of said initial internal digital approximation value is zero, then (c0) converting said initial internal digital approximation value to a corresponding initial internal analog signal; (d0) subtracting a decrement value from said initial internal digital approximation value to obtain a decremented internal digital approximation value; (e0) comparing said initial internal analog signal to said input analog signal to obtain a first test result; and (f0) generating said output digital value from either said initial internal digital approximation value or said decremented internal digital approximation value, based on said first test result; and (b1) if said least-significant bit of said initial internal digital approximation value is one, then (c1) adding an increment value to said initial internal digital approximation value to obtain an incremented internal digital approximation value; (d1) converting said incremented internal digital approximation value to a corresponding incremented internal analog signal; (e1) comparing said incremented internal analog signal to said input analog signal to obtain a second test result; and (f1) generating said output digital value from either said initial internal digital approximation value or said incremented internal digital approximation value, based on said second test result. - View Dependent Claims (24, 25, 26)
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27. An analog-to-digital converter (ADC) circuit comprising:
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a comparator having a first input coupled to a first reference voltage, a second input, and an output; a coarse ADC converter having an input coupled to an analog input signal that is to be converted into an ADC-digital-output value by the ADC circuit, said ADC-digital-output value having a plurality of N bits, and a coarse digital output, wherein said coarse ADC converter generates an M-bit decremented digital estimate corresponding to said analog input signal, on said coarse digital output, wherein M is less than N; successive-approximation logic having a first input connected to said output of said comparator, a second input connected to said coarse digital output of said coarse ADC converter, and an output; and a switched capacitor network having a sampling input, a control input, and an analog output, wherein; said sampling input is switchably coupled to said input analog signal, said control input is connected to said output of said successive-approximation logic, and said analog output is connected to said second input of said comparator. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34, 35)
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36. A method for reducing comparator-hysteresis effects while performing successive-approximation analog-to-digital conversion of an input analog signal into an output digital value, said output digital value having a plurality of N bits, said method comprising the steps of:
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(a) performing a coarse analog-to-digital conversion to generate a plurality of M bits corresponding to M most-significant bits of a digital value corresponding to said analog input signal, decremented by one, wherein M is less than N; (b) coupling said M bits to an internal digital approximation value; (c) converting said internal digital approximation value to a corresponding internal analog signal; (d) comparing said internal analog signal to a reference signal to obtain a test result; (e) generating a next-most-significant bit of said internal digital approximation value as a function of said test result; (f) successively approximating said output digital value by iteratively repeating steps (c), (d), and (e). - View Dependent Claims (37, 38, 39, 40, 41)
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42. A charge-redistribution successive-approximation analog-to-digital converter (ADC) circuit for reducing comparator-hysteresis effects while converting an input analog signal into an output digital value, said output digital value having a plurality of N bits, said circuit comprising:
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a plurality of capacitors, each one of said plurality of capacitors having a first plate and a second plate; a comparator having a first input connected to a first reference voltage signal, a second input coupled to said first plate of every one of said plurality of capacitors, and an output; a plurality of successive-approximation switches, each one of said plurality of successive-approximation switches having a common connection coupled to said second plate of a corresponding one of said plurality of capacitors and switchably coupled either to a second reference voltage or to an internal node; an input switch having a common connection coupled to said internal node and switchably coupled either to a third reference voltage or to said input analog signal; a coarse ADC converter having an input coupled to said input analog signal, and a digital output, wherein said coarse ADC converter generates a plurality of M bits corresponding to M most-significant bits of said output digital value on said digital output, wherein M is less than N; and
successive-approximation logic having a first input, a second input, and a digital output, wherein said first input is connected to said output of said comparator, said second input is connected to said digital output of said coarse ADC converter, and said digital output is coupled to control said plurality of successive-approximation switches.
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Specification