Non-volatile memory system having internal data verification test mode

• US 5,675,540 A
• Filed: 01/22/1996
• Issued: 10/07/1997
• Est. Priority Date: 01/22/1996
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Quantum Devices Inc (Micron Technology, Inc.)
• Inventors: Roohparvar, Frankie F.
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US08/589,823
• Time in Patent Office: 624 Days
• Field of Search: 365/185.22, 365/201, 365/200, 365/236, 365/185.29, 365/185.3, 365/189.02, 365/218
• US Class Current: 365/185.22
• CPC Class Codes: G06F 2201/81 Threshold
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50004 of threshold voltage
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

A memory system including means for verifying the contents of a memory cell contained in a memory array to determine if a shift in the threshold voltage level has occurred. The memory system is placed into a test mode of operation in which an internal program or erase verify operation is executed under the control of the system'"'"'s internal state machine. Once in the mode, the memory system steps through each memory cell, address by address, and reads the contents of the cell using the appropriate reference voltage for a programming or erase operation. A status register bit is set indicating successful completion of the verification operation for a block of memory cells. A register bit is also set if a cell fails the verification operation. This provides a more accurate determination of the state of a memory cell than can be achieved by performing an external read operation using read operation or data verification reference voltage levels.

Claims

1. A memory system having a standard mode of operation in which a user can program, erase, and read a memory cell, and a test mode of operation in which a non-standard mode of operation can be executed, wherein access to the test mode of operation occurs upon detection of a test mode access state different from those states which occur during the standard mode of operation, the memory system comprising:

an array of memory cells;

a test mode detector which detects the test mode access state, wherein the test mode access state is different from those states which occur during the standard mode of operation;

an internal program verify circuit which executes an internal program verify operation when the memory system is placed into an internal program verify mode of operation by the test mode detector, wherein the internal program verify circuit further comprises

a memory cell accessor which accesses a memory cell in the array;

a programmed data verification circuit which verifies data programmed into the memory cell; and

an address incrementer which increments an address of the memory cell; and

a test mode status indicator accessible to a user of the test mode which indicates success or failure of the operation executed when the memory system is placed into the internal program verify mode of operation by the test mode detector.

2. The memory system of claim 1, wherein the programmed data verification circuit further comprises:

a threshold voltage circuit which determines a threshold voltage of the memory cell; and

a comparator which compares the threshold voltage to a program operation reference voltage.

3. The memory system of claim 1, further comprising:

a controller for controlling execution of a memory erase operation which includes a plurality of memory erase sub-operations, the memory erase sub-operations including a regular memory pre-programming operation which accesses a memory cell in the array, programs the accessed memory cell with data indicative of a logic value of zero, verifies the programmed data, increments the address of the memory cell, and executes the regular pre-programming operation on a memory cell having an address corresponding to the incremented address, wherein the internal program verify circuit further comprises;

a flow controller for causing the controller to bypass one of the plurality of memory erase sub-operations.

4. The memory system of claim 3, wherein the flow controller bypasses the memory erase sub-operation in response to control parameters stored in a data storage element of the memory system.

5. The memory system of claim 4, further comprising:

a control parameter generator which generates the control parameters for bypassing the erase sub-operation in response to a control signal which initiates execution of the internal program verify operation.

6. The memory system of claim 3, wherein the flow controller bypasses a memory erase sub-operation not involved in the internal program verify operation.

7. The memory system of claim 3, wherein the memory system executes a high voltage stage in which a high voltage pulse is applied to a memory cell during a pre-programming operation, and wherein the test mode detector further comprises:

a high voltage control signal generator which generates a high voltage stage control signal which causes the high voltage stage to be bypassed when the memory system is placed into an internal program verify mode of operation by the test mode detector.

8. A memory system having a standard mode of operation in which a user can program, erase, and read a memory cell, and a test mode of operation in which a non-standard mode of operation can be executed, wherein access to the test mode of operation occurs upon detection of a test mode access state different from those states which occur during the standard mode of operation, the memory system comprising:

an array of memory cells;

a test mode detector which detects the test mode access state, wherein the test mode access state is different from those states which occur during the standard mode of operation;

an internal erase verify circuit which executes an internal erase verify operation when the memory system is placed into an internal erase verify mode of operation by the test mode detector, wherein the internal erase verify circuit further comprises

a memory cell accessor which accesses a memory cell in the array;

an erase verification circuit which verifies that the memory cell has been erased; and

an address incrementer which increments an address of the memory cell; and

a test mode status indicator accessible to a user of the test mode which indicates success or failure of the operation executed when the memory system is placed into the internal erase verify mode of operation by the test mode detector.

9. The memory system of claim 8, wherein the erase verification circuit further comprises:

a threshold voltage

circuit which determines a threshold voltage of the memory cell; and

a comparator which compares the threshold voltage to an erase operation reference voltage.

10. (Amended) The memory system of claim 8, further comprising:

a controller for controlling execution of a memory erase operation which includes a plurality of memory erase sub-operations, the memory erase sub-operations including a regular memory high voltage erase operation in which a high voltage erase operation is performed on a block of memory cells, a memory cell in the block is accessed, an erased state of the accessed memory cell is verified, the address of the memory cell is incremented, and the erased state verification operation is performed on a memory cell having an address corresponding to the incremented address, wherein the internal erase verify circuit further comprises;

a flow controller for causing the controller to bypass one of the plurality of memory erase sub-operations.

11. The memory system of claim 10, wherein the flow controller bypasses the memory erase sub-operation in response to control parameters stored in a data storage element of the memory system.

12. The memory system of claim 11, further comprising:

a control parameter generator which generates the control parameters for bypassing the erase sub-operation in response to a control signal which initiates execution of the internal erase verify operation.

13. The memory system of claim 10, wherein the flow controller bypasses a memory erase sub-operation not involved in the internal erase verify operation.

14. The memory system of claim 10, wherein the memory system executes a high voltage stage in which a high voltage pulse is applied to a memory cell during an erase operation, and wherein the test mode detection means further comprises:

a high voltage control signal generator which generates a high voltage stage control signal which causes the high voltage stage to be bypassed when the memory system is placed into an internal erase verify mode of operation by the test mode detector.

15. A memory system comprising:

an array of memory cells;

a controller for controlling execution of a memory erase operation which includes a plurality of memory erase sub-operations, the memory erase sub-operations including a regular memory pre-programming operation which accesses a memory cell in the array, programs the accessed memory cell with data indicative of a logic value of zero, verifies the programmed data, increments the address of the memory cell, and executes the regular pre-programming operation on a memory cell having an address corresponding to the incremented address; and

a control modifier which modifies the operation of the controller to cause the controller to execute an internal program verify operation on the memory cells of the memory array, the internal program verify operation including accessing a memory cell in the array, verifying data programmed into the memory cell, and incrementing an address of the memory cell.

16. The memory system of claim 15, further comprising:

an internal program verify modifier which modifies execution of the internal program verify operation so that the data programmed into the cell which is verified is data input by a user.

17. A memory system comprising:

an array of memory cells;

a controller for controlling execution of a memory erase operation which includes a plurality of memory erase sub-operations, the memory erase sub-operations including a regular memory high voltage erase operation in which a high voltage erase operation is performed on a block of memory cells, a memory cell in the block is accessed, an erased state of the accessed memory cell is verified, the address of the memory cell is incremented, and, the erased state verification operation is performed on a memory cell having an address corresponding to the incremented address; and

a control modifier which modifies the operation of the controller to cause the controller to execute an internal erase verify operation on the memory cells of the memory array, the internal erase verify operation including accessing a memory cell in the array, verifying that the memory cell has been erased, and incrementing an address of the memory cell.

18. A method of verifying a state of a memory cell contained in a memory array of a memory system, the memory system having a standard mode of operation in which a user can program, erase, and read a memory cell and a test mode of operation in which a non-standard mode of operation can be executed, wherein access to the test mode of operation occurs upon detection of a test mode access state different from those states which occur during the standard mode of operation, the method comprising:

accessing the test mode of operation;

placing the memory system into an internal program verify mode of operation;

executing an internal program verify operation when the memory system is placed into the internal program verify mode of operation, wherein the step of executing the internal program verify operation further comprises

accessing a memory cell in the array;

verifying data programmed into the memory cell; and

incrementing an address of the memory cell; and

setting a bit of a test mode status register accessible to a user of the test mode indicating success or failure of the internal program verify operation.

19. The method of claim 18, wherein the step of verifying data programmed into the memory cell further comprises:

determining a threshold voltage of the memory cell and comparing it to a program operation reference voltage.

20. The method of claim 18, wherein the memory system includes a controller for controlling execution of a memory erase operation which includes a plurality of memory erase sub-operations, the memory erase sub-operations including a regular memory pre-programming operation which accesses a memory cell in the array, programs the accessed memory cell with data indicative of a logic value of zero, verifies the programmed data, increments the address of the memory cell, and executes the regular pre-programming on a memory cell having an address corresponding to the incremented address, and wherein the method further comprises:

causing the controller to bypass a memory erase sub-operation not involved in the internal program verify operation.

21. The method of claim 20, wherein the step of causing the controller to bypass a memory erase sub-operation further comprises:

generating a control signal which causes the controller to bypass the memory sub-operation in response to placing the memory system into an internal program verify mode of operation.

22. A method of verifying a state of a memory cell contained in a memory array of a memory system, the memory system having a standard mode of operation in which a user can program, erase, and read a memory cell and a test mode of operation in which a non-standard mode of operation can be executed, wherein access to the test mode of operation occurs upon detection of a test mode access state different from those states which occur during the standard mode of operation, the method comprising:

accessing the test mode of operation;

placing the memory system into an internal erase verify mode of operation;

executing an internal erase verify operation when the memory system is placed into an internal erase verify mode of operation, wherein the step of executing the internal erase verify operation further comprises

accessing a memory cell in the array;

verifying that the memory cell has been erased; and

incrementing an address of the memory cell; and

setting a bit of a test mode status register accessible to a user of the test mode indicating success or failure of the internal erase verify operation.

23. The method of claim 22, wherein the step of verifying that the memory cell has been erased further comprises:

determining a threshold voltage of the memory cell and comparing it to an erase operation reference voltage.

24. The method of claim 22, wherein the memory system includes a controller for controlling execution of a memory erase operation which includes a plurality of memory erase sub-operations, the memory erase sub-operations including a regular memory high voltage erase operation in which a high voltage erase operation is performed on a block of memory cells, a memory cell in the block is accessed, an erased state of the accessed memory cell is verified, the address of the memory cell is incremented, and the erased state verification operation is performed on a memory cell having an address corresponding to the incremented address, and wherein the method further comprises:

causing the controller to bypass a memory erase sub-operation not involved in the internal erase verify operation.

25. The method of claim 24, wherein the step of causing the controller to bypass a memory erase sub-operation further comprises:

generating a control signal which causes the controller to bypass the memory sub-operation in response to placing the memory system into an internal erase verify mode of operation.

26. A method of verifying a state of a memory cell contained in a memory array of a memory system, the memory system including a controller which controls execution of a memory erase operation which includes a plurality of memory erase sub-operations, the memory erase sub-operations including a regular memory pre-programming operation which accesses a memory cell in the array, programs the accessed memory cell with data indicative of a logic value of zero, verifies the programmed data, increments the address of the memory cell, and executes the regular pre-programming on a memory cell having an address corresponding to the incremented address, the method comprising:

causing the controller to bypass the memory sub-operations not involved in an internal program verify operation; and

executing an internal program verify operation, wherein the step of executing the internal program verify operation further comprises;

accessing a memory cell in the array;

verifying data programmed into the memory cell; and

incrementing an address of the memory cell.

27. The method of claim 26, wherein the step of verifying data programmed into the memory cell further comprises:

determining a threshold voltage of the memory cell and comparing it to a program operation reference voltage.

28. The method of claim 26, wherein the step of executing an internal program verify operation further comprises:

setting a status register bit indicating success or failure of the internal program verify operation.

29. A method of verifying a state of a memory cell contained in a memory array of a memory system, the memory system including a controller which controls execution of a memory erase operation which includes a plurality of memory erase sub-operations, the memory erase sub-operations including a regular memory high voltage erase operation in which a high voltage erase operation is performed on a block of memory cells, a memory cell in the block is accessed, an erased state of the accessed memory cell is verified, the address of the memory cell is incremented, and the erased state verification operation is performed on a memory cell having an address corresponding to the incremented address, the method comprising:

causing the controller to bypass the memory sub-operations not involved in an internal erase verify operation; and

executing an internal erase verify operation, wherein the step of executing the internal erase verify operation further comprises;

accessing a memory cell in the array;

verifying that the memory cell has been erased; and

incrementing an address of the memory cell.

30. The method of claim 29, wherein the step of verifying that the memory cell has been erased further comprises:

determining a threshold voltage of the memory cell and comparing it to an erase operation reference voltage.

31. The method of claim 29, wherein the step of executing an internal erase verify operation further comprises:

setting a status register bit indicating success or failure of the internal erase verify operation.