Burst EDO memory device address counter

• US 5,675,549 A
• Filed: 06/01/1995
• Issued: 10/07/1997
• Est. Priority Date: 12/23/1994
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Manning, Troy A., Ong, Adrian, Wiliams, Brett L., Zagar, Paul S.
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US08/457,651
• Time in Patent Office: 859 Days
• Field of Search: 365/238.5, 365/239, 365/236, 365/233.5, 365/230.02, 365/233
• US Class Current: 365/233.5
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1024 Extended data output [EDO] mode, i.e. keeping output buffer enabled during an extended period of time
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers

Abstract

A counter comprised of two flip flops and a multiplexer produces a sequential or interleaved address sequence. The addresses produced are used to access memory elements in a Burst Extended Data Output Dynamic Random Access Memory (Burst EDO or BEDO DRAM). Input addresses in combination with a sequence select signal are logically combined to produce a multiplexer select input which selects between true and compliment outputs of a first flip flop to couple to an input of a second flip flop to specify a toggle condition for the second flip flop. Outputs of the counter are compared with outputs of an input address latch to detect the end of a burst sequence and initialize the device for another burst access. A transition of the Read/Write control line during a burst access will terminate the burst access and initialize the device for another burst access.

Claims

1. A memory device comprising a plurality of addressable memory elements, the memory device further comprising:

an address counter adapted to receive a first memory address in response to a transition of an address latch signal, and further adapted to generate a series of memory addresses in a selectable one of a plurality of predetermined burst address sequences in response to subsequent transitions of the address latch signal.

2. The memory device according to claim 1, wherein:

the plurality of predetermined burst address sequences comprises an interleaved address sequence and a linear address sequence, and any one of the plurality of predetermined burst address sequences may be selected for performing a burst access of the memory device.

3. The memory device according to claim 1, further comprising:

an address sequence select circuit electrically coupled to said address counter for selecting one of the plurality of predetermined burst address sequences.

4. The memory device according to claim 3, wherein:

the address latch signal is a column address latch signal, and said address sequence select circuit is responsive to a row address latch signal to select an address sequence from the plurality of address sequences.

5. The memory device according to claim 1, further comprising:

an output buffer, electrically coupled to the memory elements, responsive to the address latch signal to output data from the memory device after a latency of at least one cycle of the address latch signal in a burst read access.

6. A memory device comprising:

a memory array;

an address latch responsive to an address latch signal and a first input address to store the first input address;

an address counter coupled to said address latch, said address counter being responsive to the address latch signal and the first input address to provide a series of memory addresses in a predetermined sequence to said memory array; and

a comparator coupled to said address latch and to said address counter, said comparator terminating a burst access of the memory device in response to a match of the first input address from said address latch with an address of the series of memory addresses from said address counter.

7. The memory device according to claim 6, wherein:

said address latch stores a second input address in response to the address latch signal and the match of the first input address from said address latch with the address of the series of memory addresses from said address counter.

8. The memory device according to claim 6, further comprising:

an output circuit for receiving addressed data from said memory array and for driving addressed data from the memory device after a plurality of transitions of the address latch signal.

9. A memory device comprising an array of addressable memory elements, the memory device further comprising:

a counter to provide a plurality of memory addresses to the array of addressable memory elements in a predetermined address sequence in response to an input address and a plurality of transitions of a column address strobe signal;

a comparator coupled to said counter, said comparator responsive to the input address and the plurality of addresses to detect a terminal address of the predetermined address sequence; and

an output buffer coupled to the array, said output buffer responsive to the plurality of transitions of the column address strobe signal to output data after a latency of at least one cycle of the column address strobe signal.

10. A memory device comprising:

an address latch;

a sequence select circuit coupled to said address latch, said sequence select circuit responsive to a sequence control signal for selecting one of a plurality of predetermined address sequences; and

a burst address counter comprising;

a first flip flop having an output;

a second flip flop having an input; and

a multiplexer comprising a first input coupled to the output of said first flip flop, a second input coupled to a compliment of the output of said first flip flop, a third input coupled to said sequence select circuit and an output coupled to the input of said second flip flop.

11. The memory device according to claim 10, further comprising:

a comparator coupled to said address latch, said first flip flop and said second flip flop; and

a burst address counter load control circuit coupled to said burst address counter and to said comparator.

12. The memory device according to claim 10, further comprising:

a clock enable circuit coupled to a clock input of said second flip flop and to an output of said multiplexer.

13. An integrated circuit device having an address counter, the address counter comprising:

a first flip flop;

a second flip flop; and

a multiplexer coupled to said first flip flop and said second flip flop to selectively couple one of either an output of said first flip flop or a complement of the output of said first flip flop to an input of said second flip flop to specify a toggle condition for said second flip flop.

14. The device according to claim 13, further comprising:

an array of dynamic random access memory elements wherein said address counter determines at least a portion of a column address of said array.

15. The device according to claim 13, further comprising:

an address latch to latch an external address signal; and

a multiplexer control circuit, coupled to said multiplexer, responsive to a latched address signal from said address latch to select between the output of said first flip flop and the complement of the output of said first flip flop for coupling to the input of said second flip flop.

16. The device according to claim 13, further comprising:

a multiplexer control circuit, coupled to said multiplexer, responsive to a sequence control signal to select between the output of said first flip flop and the complement of the output of said first flip flop for coupling to the input of said second flip flop.

17. The device according to claim 13, further comprising:

a clock enable circuit coupled to the input of said second flip flop and to said multiplexer.

18. The device according to claim 17, wherein said clock enable circuit comprises:

a latch having an input coupled to said multiplexer; and

a logic gate coupled to an output of said latch and to said second flip flop, said logic gate enabled by the output of said latch to pass a clock signal to said second flip flop.

19. A counter for use in an integrated memory device comprising:

a first flip flop;

a second flip flop; and

a multiplexer coupled to said first flip flop and said second flip flop, said multiplexer responsive to a select signal to couple an output of said first flip flop or a compliment of the output of said first flip flop to an input of said second flip flop to specify a toggle condition for said second flip flop.

20. A control circuit for a counter used in an integrated memory device, comprising:

a sequence control circuit, coupled to the counter and an initial count register, responsive to a sequence control signal for selecting one of a plurality of predetermined address sequences; and

a comparator coupled to an output of the counter and to the initial count register, wherein the counter is loaded in response to an output of said comparator indicating a match between the output of the counter and a corresponding output of the initial count register, and the counter counts in a sequence determined by said sequence control circuit.

21. A method of performing a burst access of a memory device, comprising:

loading a burst address counter with a first initial address;

accessing a first memory element at the first initial address;

advancing the burst address counter;

accessing a second memory element at an address provided by the burst address counter;

comparing the first initial address with the address provided by the burst address counter; and

terminating the burst access in response to a match of the first initial address with the address provided by the burst address counter.

22. The method according to claim 21, further comprising:

loading the burst address counter with a second initial address in response to a match of the first address with the address provided by the burst address counter.

23. In a memory device having an address input, an address strobe input, a write control input and an address counter, the address counter comprising a first flip flop, a second flip flop and a multiplexer, a method of accessing a memory element of the memory device, comprising:

loading a portion of a first address into the first flip flop and the second flip flop in response to an address strobe received on the address strobe input and the first address received on the address input;

coupling an output of the first flip flop to an input of the second flip flop through the multiplexer;

toggling an output of the second flip flop in response to the output of the first flip flop received from the multiplexer; and

accessing the memory element at a second address determined at least in part by the output of the first flip flop and the output of the second flip flop.

24. The method according to claim 23, further comprising:

coupling a compliment of the output of the first flip flop to the input of the second flip flop through the multiplexer in response to an address sequence control signal and a least significant bit of the first address.

25. The method according to claim 23, further comprising:

terminating a burst access of the memory device in response to an output of the first flip flop and an output of the second flip flop matching a corresponding portion of the first address.

26. The method according to claim 23, further comprising:

loading a portion of a third address into the first flip flop and the second flip flop in response to a further address strobe received on the address strobe input, the third address received on the address input, and the output of the first flip flop and the output of the second flip flop matching a corresponding portion of the first address received on the address input.

27. The method according to claim 23, further comprising:

terminating a burst access of the memory device in response to a transition of a write control signal received on the write control input.