High speed serial link for fully duplexed data communication

• US 5,675,584 A
• Filed: 12/29/1995
• Issued: 10/07/1997
• Est. Priority Date: 06/06/1994
• Status: Expired due to Term

• Current Assignee: Deog-Kyoon Jeong, Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Deog-Kyoon Jeong, Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Jeong, Deog-Kyoon
• Primary Examiner(s): BLUM, RUSSELL
• Application Number:
  US08/580,700
• Time in Patent Office: 648 Days
• Field of Search: 370/24, 370/27, 370/28, 370/32, 370/85.1, 370/85.13, 370/100.1, 370/112, 370/79, 370/282, 370/284, 370/466, 370/503, 370/535, 375/219, 375/220, 327/407, 327/408, 327/415, 327/416
• US Class Current: 370/284
• CPC Class Codes: H03K 19/018592 with a bidirectional operation
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/0895 Details of the current generators H03L7/0893 takes precedence
• CPC Class Codes: H03L 7/0996 Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator
• CPC Class Codes: H03M 9/00 Parallel/series conversion or vice versa digital stores in which the information is moved stepwise per se G11C19/00
• CPC Class Codes: H04J 3/047 Distributors with transistors or integrated circuits
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0278 Arrangements for impedance matching
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end
• CPC Class Codes: H04L 25/085 Arrangements for reducing interference in line transmission systems, e.g. by differential transmission
• CPC Class Codes: H04L 5/1423 for simultaneous baseband signals
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
• CPC Class Codes: H04L 7/0338 the correction of the phase error being performed by a feed forward loop

Abstract

A system for converting between parallel data and serial data is described. In the system (10), individual bits of the parallel data (12) are latched into individual registers (117). Each register (117) is coupled to a corresponding AND gate (110) which is also connected to receive phased clock signals. The output terminals of the AND gates (110) are connected to an OR gate (115). Using the system, with appropriately phased clocks, the parallel data is converted into serial data.

Claims

1. A system for full duplex interfacing of parallel devices with a serial communications link comprising:

a clock generator for generating a series of subfrequency clocks from a reference clock signal, and for supplying each subfrequency clock on a corresponding conductor;

a transmitter coupled to receive parallel data from a parallel device and coupled to receive the series of subfrequency clocks and in response thereto supply as an output signal a serial data stream;

a bidirectional buffer coupled to the transmitter and to the serial communications link for supplying the serial data stream from the transmitter to the serial communications link, and for detecting serial data on the link;

a data sampler coupled to the clock generator and to the bidirectional buffer for receiving data from the serial communications link in response to a plurality of the subfrequency clocks; and

a receiver for converting the received serial data to parallel data and supplying it to a parallel device.

2. The system of claim 1 wherein the bidirectional buffer receives a mixed signal, comprising the output signal and an incoming signal, from the serial communications link, recovers the incoming signal from the mixed signal, and provides the incoming signal, without the output signal, to the data sampler.

3. The system of claim 1 wherein a clock of the receiver is not synchronized with a clock of a remote transmitter sending serial data stream on the communications link, and the receiver synchronizes itself according to the serial data stream on the communications link.

4. The system of claim 3 wherein the receiver compensates and resynchronizes itself for phase drifts in the serial data stream.

5. The system of claim 1 wherein the serial data stream on the communications link represents parallel data words having frame boundaries, and the receiver reconstructs the parallel data words from the serial data stream.

6. The system of claim 1 wherein in response to the series of subfrequency clocks, the data sampler oversamples the incoming signal and generates sampled bits of data at evenly divided time intervals.

7. The system of claim 6 wherein the receiver receives the sampled bits of data, calculates a frame boundary for a word of the sampled bits of data, and selects recovered data bits from the sampled bits of data to output to the parallel device.

8. The system of claim 1 where every serial bit in the serial data stream is sampled at least at three different times to allow the receiver to track phase changes in the serial data stream.

9. The system of claim 1 wherein each of the series of subfrequency clock signals has a different phase than every other clock signal, wherein the series of subfrequency clock signals comprise the reference clock signal divided into a plurality of phases.

10. The system of claim 1 wherein the transmitter is coupled to receive the series of subfrequency clocks, at least one subfrequency clock for each bit of the parallel data and each clock having a different phase, whereby the transmitter outputs one bit of the parallel data at each phase of the series of subfrequency clocks to generate the serial data stream.

11. The system of claim 1 wherein the transmitter outputs outgoing serial data across the serial communications link simultaneously when the receiver is receiving incoming serial data from the serial communications link, wherein the outgoing serial data and the incoming serial data are simultaneously resident on the serial communication link.

12. The system of claim 1 wherein the clock generator further comprises two parallel buffers wherein the two parallel buffers provide a first group of the subfrequency clocks and a second group of the subfrequency clocks.

13. The system of claim 1 wherein the clock generator further comprises a loop filter.

14. A system for full duplex interfacing of parallel devices with a serial communications link comprising:

a clock generator for generating a series of subfrequency clocks from a reference clock signal, and for supplying each subfrequency clock on a corresponding conductor wherein the series of subfrequency clocks are distributed on adjacent, parallel conductors, and in order to reduce capacitive coupling between the conductors and minimize clock skew, the series of subfrequency clocks are arranged so that during a transition of a clock on one conductor, signals on neighboring conductors on each side have settled to a static state;

a transmitter coupled to receive parallel data from a parallel device and coupled to receive the series of subfrequency clocks and in response thereto supply as an output signal a serial data stream;

a bidirectional buffer coupled to the transmitter and to the serial communications link for supplying the serial data stream from the transmitter to the serial communications link, and for detecting serial data on the link;

a data sampler coupled to the bidirectional buffer for receiving data from the serial communications link; and

a receiver for converting the data from serial to parallel and supplying it to a parallel device.

15. The system of claim 14 further comprising:

at least one dummy conductor, adjacent and substantially parallel to the conductors, and positioned at an edge of the conductors, providing symmetrical capacitive coupling for a conductor at the edge of the conductors.

16. A system for transferring and receiving data on a serial transmission line comprising:

a clock generator for generating a plurality of clock signals, wherein each clock signal is a subfrequency of a reference clock and has a different phase;

a transmitter coupled to receive parallel data, and serially outputs the parallel data as an outgoing data stream to the serial transmission line, wherein each bit in the outgoing serial data stream is output in response to one of the plurality of clock signals;

a receiver coupled to receive an incoming data stream from the serial transmission line, wherein the serial transmission line contains a mixed signal having the outgoing data stream and the incoming data stream, whereby the receiver oversamples the incoming data stream to obtain a plurality of sampled bits, each sampled bit is sampled in response to one of the plurality of clock signals; and

a bidirectional buffer, coupled between the transmitter and the serial transmission line and between the receiver and the serial transmission line, wherein the bidirectional buffer subtracts the outgoing data stream from the mixed signal to obtain the incoming data stream for the receiver.

17. The system of claim 16 wherein the receiver converts the incoming data stream into parallel data.

18. The system of claim 16 wherein the receiver determines a phase of the incoming data stream, and based on the phase, converts a subdivision of the plurality of sampled bits into parallel data.

19. The system of claim 16 wherein a clock signal of a remote transmitter generating the incoming data stream for the serial transmission line is not synchronized with the plurality of clock signals of the clock generator.

20. A method for full duplex interfacing of parallel devices with a serial communications link comprising the steps of:

providing a plurality of clock signals, each being a subfrequency of a reference clock and having a different phase from every other clock;

using signals selected from the plurality of clock signals, converting parallel outgoing data into an outgoing serial data stream, wherein each bit of the parallel data is converted into a bit of the outgoing serial data stream in response to one of the plurality of clock signals;

outputting the outgoing serial data stream through a bidirectional buffer to a serial communications line;

recovering an incoming serial data stream from the serial communications line and through the bidirectional buffer by subtracting the outgoing serial data stream from a mixed data serial stream on the serial communications line; and

converting the incoming serial data stream to a parallel data stream in response to at least one clock signal selected from the plurality of clock signals.

21. The method of claim 20 wherein the step of converting the incoming serial data stream comprises the steps of:

oversampling the incoming serial data stream in response to the plurality of clock signals, and providing a plurality of sampled bits representative of the incoming serial data stream;

determining the phase and word boundaries of data in the incoming data stream;

based on the phase and word boundaries, selecting a portion of the plurality of sampled bits; and

outputting the portion of the plurality of sampled bits in parallel as recovered data.

22. The method of claim 20 further comprising the steps of:

providing known data on the serial communications line;

receiving the known data in a receiver;

synchronizing the receiver using the known data to determine phase and word boundaries of the known data; and

recovering the known data.

23. A system for interfacing parallel devices with a serial communications link comprising:

a clock generator for generating a plurality of subfrequency clocks from a reference clock signal, and for supplying each subfrequency clock on a corresponding conductor;

a transmitter coupled to receive parallel data, the transmitter comprising;

a plurality of AND gates, each AND gate having an output node, each AND gate coupled to receive a primary subfrequency clock of the plurality of subfrequency clocks, and to receive a data bit of the parallel data; and

an OR gate having an output node for supplying a serial data stream, the OR gate having a plurality of input nodes coupled to each of the output nodes of the plurality of AND gates;

a bidirectional buffer coupled to the transmitter and to the serial communications link for supplying the serial data stream from the transmitter to the serial communications link, and for detecting serial data on the link;

a data sampler coupled to the clock generator and to the bidirectional buffer for receiving data from the serial communications link in response to a plurality of the subfrequency; and

a receiver for converting the data from serial to parallel and supplying it to a parallel device.

24. The system of claim 23 wherein each AND gate is further coupled to receive a complementary signal of a secondary subfrequency clock of the plurality of subfrequency clocks, wherein for each AND gate the coupled secondary subfrequency clock is different from the coupled primary subfrequency clock.

25. The system of claim 23 wherein the transmitter further comprises:

a first register having a plurality of storage locations for temporarily storing the parallel data; and

a second register, coupled to a portion of the storage locations of the first register, for latching data from the portion of the storage locations of the first register.