Coding method, semiconductor memory for implementing coding method, decoder for semiconductor memory and method for identification of hand-written characters

• US 5,675,668 A
• Filed: 04/08/1993
• Issued: 10/07/1997
• Est. Priority Date: 04/08/1992
• Status: Expired due to Fees

• Current Assignee: Kawasaki MicroElectronics (Megachips Corporation)
• Original Assignee: Kawaski Steel Corporation
• Inventors: Yoneda, Masato
• Primary Examiner(s): Boudreau, Leo
• Assistant Examiner(s): KELLEY, CHRISTOPHER S
• Application Number:
  US08/044,195
• Time in Patent Office: 1,643 Days
• Field of Search: 382/37, 382/56, 382/14, 382/21, 382/24, 382/232, 382/233, 382/240, 382/246, 382/249, 358/467, 358/470
• US Class Current: 382/240
• CPC Class Codes: G06F 18/24323 Tree-organised classifiers
• CPC Class Codes: G06V 10/75 Organisation of the matching processes, e.g. simultaneous or sequential comparisons of image or video features; Coarse-fine approaches, e.g. multi-scale approaches; using context analysis; Selection of dictionaries

Abstract

The present invention related to a coding method suited to obtain at a high speed a code number determined according to a sequence of arrangement of a plurality of texts which are arranged in a tree structure and output the code number and a semiconductor memory for implementing the coding method wherein a node number is assigned to each of nodes of the tree structure and a node to which the retrieval should advance is obtained in accordance with both a text entered and a node number of a node where the retrieval currently stays.

Claims

1. A semiconductor memory, comprising:

a plurality of memory areas, the plurality of memory areas divided into a plurality of memory blocks, each memory area comprising a plurality of memory cells, the plurality of memory cells equal to a predetermined number of bits;

a retrieval data input terminal into which retrieval data is input;

a correspondence detection circuit comprising a plurality of correspondence detection sub-circuits each for storing a plurality of comparison data corresponding to respective ones of the plurality of memory areas constituting the plurality of memory blocks, wherein said plurality of correspondence detection sub-circuits compares said input retrieval data and each of said plurality of comparison data simultaneously and wherein the correspondence detection circuit outputs a selection signal selecting one of said plurality of memory areas corresponding to said comparison data which matches said input retrieval data;

a plurality of sense amplifiers equal in number to the predetermined number of bits for amplifying and outputting contents stored in said plurality of memory cells; and

a block selection circuit for selecting one of said plurality of blocks, the block selection circuit selecting the memory block containing the memory area selected by said selection signal and connecting the plurality of memory cells in said selection to said selected one plurality of sense amplifiers.

2. A semiconductor memory according to claim 1, wherein said block selection circuit comprises a plurality of block connecting circuits each corresponding to an associated one of said plurality of correspondence detection sub-circuits, said plurality of block connecting circuits being each responsive to the selection signal outputted from the associated correspondence detection sub-circuit for connecting the memory cell in the associated block to the associated sense amplifier.

3. A semiconductor memory according to claim 1, wherein a comparison between the retrieval data and the comparison data is performed simultaneously in all of said plurality of correspondence detection sub-circuits, and a readout of contents of the memory areas is carried out in accordance with an operation of only the block to which the memory area storing the content to be read belongs, among said plurality of blocks.