Cache memory system and method for selectively removing stale aliased entries
First Claim
1. A cache memory system comprising:
- a processor;
a cache, said cache comprising a plurality of entries, each entry of said cache comprising a tag field connected to said processor by at least one virtual address line and a data field, each entry of said cache further comprising a status field containing at least one bit for indicating possible membership of the corresponding entry in a class of entries requiring selective flushing from said cache, said class of entries comprising entries which are potential aliases;
said processor including means, coupled to the status field of each of the cache entries, for setting the at least one bit of the status field of a cache entry to indicate membership of that entry in said cache in the class of entries requiring selective flushing from said cache, said means for setting further comprising;
a translation look-aside buffer, said translation look-aside buffer comprising a plurality of entries corresponding to said plurality of entries of said cache, each entry of said translation lookaside buffer comprising a status field containing an appropriate value of the at least one bit of the status field of a corresponding cache entry; and
fill means for loading the at least one bit of the status field of a cache entry with said status value from a corresponding location in said translation lookaside buffer as said cache entry is written to said cache; and
said cache memory system further comprising means, connected to said cache, for selectively flushing an entry in said cache having the at least one bit of its status field set to indicate membership of that entry in the class of entries that are potential aliases.
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Accused Products
Abstract
A cache memory system and method for selectively removing stale "aliased" entries, which arise when portions of several address spaces are mapped into a single region of real memory, from a virtually addressed cache, are described. The cache memory system includes a central processor unit (CPU) and a first-level cache on an integrated circuit chip. The CPU receives tag and data information from the first level cache via virtual address lines and data lines respectively. An off-chip second level cache is additionally coupled to provide data to the data lines. The CPU is coupled to a translation lookaside buffer (TLB) via the virtual address lines, while the second level cache is coupled to the TLB via physical address lines. The first and second level caches each comprise a plurality of entries. Each of the entries includes a status bit, indicating possible membership in a class of entries that might require flushing. Address translation database entries (page table entries or translation lookaside buffer (TLB) entries) are augmented with a field that contains the appropriate value of the status bits of each first and second level cache entry. Status bits are set for any page in which stale aliases may potentially occur (i.e., those shared pages that can be modified by at least one process or device). The cache-fill mechanism includes a path combining the status bits with the data being loaded into the first-level cache.
37 Citations
12 Claims
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1. A cache memory system comprising:
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a processor; a cache, said cache comprising a plurality of entries, each entry of said cache comprising a tag field connected to said processor by at least one virtual address line and a data field, each entry of said cache further comprising a status field containing at least one bit for indicating possible membership of the corresponding entry in a class of entries requiring selective flushing from said cache, said class of entries comprising entries which are potential aliases; said processor including means, coupled to the status field of each of the cache entries, for setting the at least one bit of the status field of a cache entry to indicate membership of that entry in said cache in the class of entries requiring selective flushing from said cache, said means for setting further comprising; a translation look-aside buffer, said translation look-aside buffer comprising a plurality of entries corresponding to said plurality of entries of said cache, each entry of said translation lookaside buffer comprising a status field containing an appropriate value of the at least one bit of the status field of a corresponding cache entry; and fill means for loading the at least one bit of the status field of a cache entry with said status value from a corresponding location in said translation lookaside buffer as said cache entry is written to said cache; and said cache memory system further comprising means, connected to said cache, for selectively flushing an entry in said cache having the at least one bit of its status field set to indicate membership of that entry in the class of entries that are potential aliases. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for operating a cache memory system having a processor and a cache, said cache having a plurality of entries, each of said entries having a tag field connected to the processor by at least one virtual address line, each of said entries further comprising a data field, said method comprising the steps of:
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storing a status value in a status field in each of the entries of the cache, each status field comprising at least one bit for indicating the membership of the corresponding entry in a class of entries requiring selective flushing from the cache, said class comprising entries which are potential aliases; setting the at least one bit of the status field of a cache entry to indicate membership of that entry in said cache in the class of entries requiring selective flushing from said cache, said setting step further comprising the steps of; providing a translation look-aside buffer, said translation look-aside buffer comprising a plurality of entries corresponding to said plurality of entries of said cache, each entry of said translation lookaside buffer comprising a status field containing an appropriate value of the at least one bit of the status field of a cache entry; and loading the at least one bit of the status field of a cache entry with said status value from a corresponding location in said translation lookaside buffer as said cache entry is written to said cache; and said method of operating further comprising the step of, responsive to said status field of each one of said cache entries, selectively flushing the corresponding entry from said cache. - View Dependent Claims (10, 11, 12)
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Specification