Power control of circuit modules within an integrated circuit

• US 5,675,808 A
• Filed: 11/02/1994
• Issued: 10/07/1997
• Est. Priority Date: 11/02/1994
• Status: Expired due to Term

• Current Assignee: Intellectual Ventures I LLC (Intellectual Ventures LLC)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Gulick, Dele E., Hogan, Michael, Hewitt, Larry D., Norris, David
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US08/333,537
• Time in Patent Office: 1,070 Days
• Field of Search: 395/250, 395/550, 395/800, 395/428, 395/750, 364/707, 365/226, 365/227, 307/66, 327/291, 327/299
• US Class Current: 713/322
• CPC Class Codes: G06F 7/026 Magnitude comparison, i.e. determining the relative order of operands based on their numerical value, e.g. window comparator
• CPC Class Codes: H03K 23/68 with a base which is a non-integer

Abstract

A power control and memory refresh rate management circuit is described. The power control circuit provides circuitry for selectively disabling or enabling modular logic circuit blocks within a VLSI integrated circuit under program control from an external processor, or for suspended circuit operation in general. In low-power modes external memory refresh signal generation circuits are provided with a low-frequency oscillator signal to conserve power.

Claims

1. A monolithic integrated circuit, including a plurality of modular logic circuits, each module having a defined function pertaining to a corresponding plurality of operations to be performed by said integrated circuit in response to circuit control signals, said integrated circuit further including a clock signal input circuit for receiving an input clock signal from an external source;

a clock signal distribution circuit for distributing a plurality of individual clock signals to said modular logic circuits; and

a clock control circuit for selectively enabling or disabling selected clock signals for each of said modular logic circuits;

wherein said clock control circuit further comprises a programmable register including a plurality of power control bit positions and a power control logic circuit responsive to the states of said bit positions to selectively enable or disable individual clock signals distributed to selected individual modular logic circuits within said integrated circuit.

2. The circuit of claim 1, wherein said clock control circuit includes a circuit for generating a modular logic circuit power control signal and a logic circuit responsive to the modular power control signal for selectively disabling clock input signals to selected modular logic circuits.

3. The circuit of claim 1, wherein said clock control circuit further comprises a power-down delay circuit for delaying the disabling of clock signals for a defined period when transitioning from power-up to power-down status.

4. The circuit of claim 1, wherein said clock control circuit further comprises a power-up delay circuit for delaying the enabling of said clock signals distributed to said selected modular logic circuits for a defined period before transitioning from power-down to power-up status.

5. The circuit of claim 1, further comprising a shut-down logic circuit for generating a circuit shut-down signal;

and an external oscillator disabling circuit, responsive to the shut-down signal to disable the external oscillator.

6. The circuit of claim 5, further comprising a delay circuit responsive to the shut-down signal for delaying the disabling of the oscillator for a prescribed period.

7. The circuit of claim 5, wherein said circuit includes a plurality of input/output accessible registers, and wherein said circuit further comprises:

means for maintaining said registers as readable and writable during shut-down mode.

8. The circuit of claim 5, further comprising:

a second clock input terminal for receiving a low frequency input clock signal from a second external oscillator source;

an external memory interface circuit for providing memory refresh signals to external memory devices, said memory interface circuit receiving a clock signal from said clock signal distribution circuit; and

wherein said clock distribution circuit further comprises an external memory clock selection circuit for selectively providing said memory interface circuit with the low-frequency clock signal in response to the circuit shut-down signal.

9. The circuit of claim 1, wherein said integrated circuit includes a plurality of input-output terminals for interfacing to external circuitry, and wherein said integrated circuit further comprises:

a circuit suspend mode input for receiving a suspend signal from an external controlling device; and

a suspend mode logic circuit responsive to the suspend signal to disable the external oscillator, and to disable selected input-output terminals of said integrated circuit.

10. The circuit of claim 9, wherein said suspend mode logic circuit includes means for forcing selected output terminals to a high-impedance state.

11. The circuit of claim 9, wherein said suspend mode logic circuit includes means for forcing selected input-output terminals to either a logic high or logic low state.

12. The circuit of claim 9, further comprising:

a second clock input terminal for receiving a low-frequency input clock signal from a second external source;

an external memory interface circuit for providing memory refresh signals to external memory devices;

said memory interface circuit receiving a clock signal from said clock distribution circuit; and

wherein said clock distribution circuit further comprises an external memory clock selection circuit for providing said memory interface circuit with the low-frequency clock signal in response to the suspend mode signal.

13. A monolithic integrated circuit, including a plurality of modular logic circuits, each module having a defined function pertaining to a corresponding plurality of operations to be performed by said integrated circuit in response to circuit control signals, said integrated circuit further including a clock signal input circuit for receiving an input clock signal from an external source, a clock signal distribution circuit for distributing a plurality of individual clock signals to said modular logic circuits, and a clock control circuit for selectively enabling or disabling selected clock signals for each of said modular logic circuits;

wherein said clock control circuit further comprises a power-up delay circuit for delaying the enabling of said clock signals distributed to said selected modular logic circuits for a defined period to ensure that said input clock signal external source is stable prior to transitioning from power-down to power-up status;

wherein said clock control circuit further comprises a programmable register including a plurality of power control bit positions and a power control logic circuit responsive to the states of said bit positions to selectively enable or disable individual clock signals distributed to selected individual modular logic circuits within said integrated circuit.