Overflow and underflow processing circuit of a binary adder
First Claim
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1. An overflow-underflow processing circuit for processing an overflow/underflow signal which is generated when binary values are added with an adder, comprising:
- generation means for generating a plurality of candidate signals for an overflow/underflow determination signal according to at least one signal including a plurality of the most significant bits of said binary values, andoverflow/underflow signal selecting means for selecting any of said candidate signals generated by said generation means in response to one of a carry-out signal and a sum signal of said adder.
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Abstract
Two input data X (7), Y (7), . . . , X (0), Y (0) are input to a plurality of full adders, and an overflow/underflow signal of each full adder is input to a full adder of a higher level. An overflow/underflow signal Co of the full adder of the most significant bit and data Y (7) are applied to an EXOR gate to obtain an exclusive OR. According to an output signal of the EXOR gate, an added output of each full adder or data Y (7) is selected by a selector, whereby a straight binary signal is output.
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Citations
11 Claims
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1. An overflow-underflow processing circuit for processing an overflow/underflow signal which is generated when binary values are added with an adder, comprising:
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generation means for generating a plurality of candidate signals for an overflow/underflow determination signal according to at least one signal including a plurality of the most significant bits of said binary values, and overflow/underflow signal selecting means for selecting any of said candidate signals generated by said generation means in response to one of a carry-out signal and a sum signal of said adder. - View Dependent Claims (2)
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3. An overflow-underflow processing circuit adding a plurality of data of N bits with an adder to limit the number of digits to N-m bits for processing an overflow/underflow signal, said overflow-underflow processing circuit comprising:
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generation means for generating in advance a plurality of candidate signals indicating a presence of an overflow/underflow according to at least one signal including a plurality of the most significant n bits of said plurality of data of N bits, and overflow/underflow determination signal generation means responsive to one of a carry-out signal and a sum signal of said adder for selecting one of said plurality of candidate signals as an overflow/underflow determination signal.
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4. An overflow-underflow processing circuit of a binary adder comprising:
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add means for adding N-bit straight binary data and N-bit two'"'"'s complement, and overflow/underflow determination signal generation means for providing an overflow/underflow determination signal by an exclusive OR of the most significant bit of said two'"'"'s complement and a carry out signal output from said add means. - View Dependent Claims (5)
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6. An overflow-underflow processing circuit of a binary adder, comprising:
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a carry save type 3-input add means for adding a N-bit straight binary signal, a N-bit two'"'"'s complement signal, and a signal having said N-bit two'"'"'s complement signal multiplied by a constant coefficient, and overflow/underflow determination means for making determination of an overflow/underflow according to an exclusive OR signal of a carry out signal obtained from a result of adding a sum signal of each of the most significant bit of said 3 inputs and a carry-out signal which is the second most significant bits of said 3 inputs added by said add means, and a sign bit of two'"'"'s complement signal.
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7. An overflow-underflow processing circuit of a binary adder comprising:
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a carry save type 3-input add means for adding N-bit straight binary A, (N-1) bit two'"'"'s complement B, and (N-2) bit two'"'"'s complement C to output N-bit straight binary D, and overflow/underflow determination means for making determination of an overflow/underflow with the logic of;
space="preserve" listing-type="equation">/Co·
An·
(Bn·
Cn)+Co·
/An·
(/Bn+/Cnwhere Co is a carry-out signal output by said 3-input add means adding a sum signal of the respective most significant bits An, Bn and Cn of said 3 inputs and a carry-out signal which is generated when the second most significant bits of said 3 inputs are added.
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8. An overflow-underflow processing circuit of a binary adder comprising:
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a carry save type 3-input adder for adding N-bit straight binary A, (N-1) bit two'"'"'s complement B, and (N-2) bit two'"'"'s complement C for providing a N-bit straight binary D, and overflow/underflow determination means for making determination of an overflow/underflow by selecting any of /Co·
An (Bn·
Cn) and Co·
/An·
(/Bn+/Cn) where Co is a carry-out signal output by said 3-input adder adding a sum signal of the respective most significant bits An, Bn and Cn of said 3 inputs and a carry-out signal which is generated when the inputs of the second most significant bits of said 3 inputs are added.
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9. An adder for adding two'"'"'s complements of horizontal direction N bits and vertical direction N bits with each other to obtain an output of N-1 bit two'"'"'s complement, said adder comprising:
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overflow/underflow presence determination means for making determination of an overflow/underflow on the basis of the most significant bits of said horizontal and vertical direction N bits and the value of the second most significant bits of said horizontal and vertical direction N bits, and output prediction value generation means for providing as an output prediction value any of the value of the most significant bit and the second most significant bit of said vertical direction N bits and the value of the most significant bit and the second most significant bit of said horizontal direction N bits according to a determination output of said overflow/underflow presence determination means. - View Dependent Claims (10, 11)
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Specification