Integrated circuit memory using fusible links in a scan chain

• US 5,677,917 A
• Filed: 04/29/1996
• Issued: 10/14/1997
• Est. Priority Date: 04/29/1996
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc., Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Haverkos, Todd D., Wheelus, Richard A., Jones, Kenneth W.
• Primary Examiner(s): Nguyen, Hoa T.
• Application Number:
  US08/641,151
• Time in Patent Office: 533 Days
• Field of Search: 371/22.3, 371/21.1, 371/22.2, 371/22.5, 371/22.6, 371/22.1
• US Class Current: 714/726
• CPC Class Codes: G11C 29/835 with roll call arrangements for redundant substitutions

Abstract

An integrated circuit memory (140) includes programmable fuses (20) coupled to scannable flip-flops (25). The programmable fuses (20) and scannable flip-flops (25) are implemented in a scan chain, and are used to program specific information about the integrated circuit memory (140), such as for example, repair (redundancy) information, wafer lot number and wafer number, die position on the wafer, or any other information that would be useful during or after package testing.

Claims

1. An integrated circuit memory implementing a scan test, comprising:

a plurality of fuse circuits for storing predetermined information concerning the integrated circuit memory; and

a plurality of latch circuits, coupled to the plurality of fuse circuits, each fuse circuit of the plurality of fuse circuit coupled to a corresponding one of the plurality of latch circuits, the plurality of latch circuits serially coupled to form a scan chain for selectively providing the predetermined information when the integrated circuit memory is in a test mode.

2. The integrated circuit memory of claim 1, wherein a fuse circuit of the plurality of fuse circuits comprises:

a fusible link having a first terminal coupled to a first supply voltage terminal, and a second terminal;

a first transistor having a first current electrode coupled to the second terminal of the fusible link, a control electrode for receiving a bias voltage, and a second current electrode coupled to a second supply voltage terminal;

a second transistor having a first current electrode coupled to the second terminal of the fusible link, a control electrode, and a second current electrode coupled to the second supply voltage terminal; and

a first inverter having an input terminal coupled to the second terminal of the fusible link, and an output terminal coupled to the control electrode of the second transistor.

3. The integrated circuit memory of claim 2, wherein the fuse circuit further comprises:

a second inverter having an input terminal coupled to output terminal of the first inverter, and an output terminal;

a third transistor having a first current electrode coupled to the first supply voltage terminal, a control electrode coupled to the output terminal of the second inverter, and a second current electrode;

a fourth transistor having a first current electrode coupled to the second current electrode of the third transistor, a control electrode for receiving a first input signal, and a second current electrode;

a fifth transistor having a first current electrode coupled to the second current electrode of the fourth transistor, a control electrode for receiving a second input signal, and a second current electrode for providing the predetermined information; and

a sixth transistor having a first current electrode coupled to the second current electrode of the fifth transistor, a control electrode coupled to the output terminal of the second inverter, and a second current electrode coupled to the second supply voltage terminal.

4. The integrated circuit memory of claim 2, wherein the fusible link is a laser blowable fusible link.

5. The integrated circuit memory of claim 1, wherein a latch circuit of the plurality of latch circuits comprises a flip-flop circuit having a first input terminal coupled to the fuse circuit for receiving a portion of the predetermined information, a second input terminal for receiving a test data in signal, a third input terminal for receiving a test mode signal, a fourth input terminal for receiving a clock signal, and an output terminal for providing a scan out signal representative of one of the predetermined information or the test data in signal in response to the test mode signal.

6. The integrated circuit memory of claim 1, further comprising:

a shift register having an input terminal for receiving a shifted-in test data in signal, a plurality of serially connected registers, and a plurality of output terminals for providing an address signal;

a decoder circuit coupled to the shift register, for receiving the address signal, and in response, providing a decoded address signal;

wherein the the plurality of fuse circuits are addressable fuse circuits for providing the predetermined information in response to the decoded address signal; and

wherein the plurality of latch circuits are for receiving in parallel the predetermined information, and serially shifting the predetermined information from the addressable fuse circuits, and for providing the shifted predetermined information in response to the integrated circuit memory being in the test mode.

7. The integrated circuit memory of claim 6, wherein the addressable fuse circuits are arranged as an N×

M bit fuse array, where N and M are integers, and the plurality of latch circuits receive M bits in parallel from a predetermined location of the addressable fuse circuits depending on the decoded address signal.

8. The integrated circuit memory of claim 1, wherein the predetermined information is redundancy information.

9. An integrated circuit memory with redundancy, comprising:

a shift register having an input terminal for receiving an input signal, a plurality of serially connected registers, and an output terminal for providing an address signal;

a decoder circuit coupled to the shift register, for receiving the address signal, and in response, providing a decoded address signal;

a plurality of addressable fuse circuits, for providing stored fuse information in response to the decoded address signal, the stored fuse information including predetermined information concerning the integrated circuit memory; and

a plurality of serially connected latch circuits forming a scan chain, each latch circuit correspondingly, coupled to one of the addressable fuse circuits, for providing the stored fuse information in response to the integrated circuit memory being in a test mode.

10. The integrated circuit memory of claim 9, wherein each of the addressable fuse circuits comprises:

a fusible link having a first terminal coupled to a first supply voltage terminal, and a second terminal;

a first transistor having a first current electrode coupled to the second terminal of the fusible link, a control electrode for receiving a bias voltage, and a second current electrode coupled to a second supply voltage terminal;

a second transistor having a first current electrode coupled to the second terminal of the fusible link, a control electrode, and a second current electrode coupled to the second supply voltage terminal;

a first inverter having an input terminal coupled to the second terminal of the fusible link, and an output terminal coupled to the control electrode of the second transistor;

a second inverter having an input terminal coupled to output terminal of the first inverter, and an output terminal;

a third transistor having a first current electrode coupled to the first supply voltage terminal, a control electrode coupled to the output terminal of the second inverter, and a second current electrode;

a fourth transistor having a first current electrode coupled to the second current electrode of the third transistor, a control electrode for receiving a first input signal, and a second current electrode;

a fifth transistor having a first current electrode coupled to the second current electrode of the fourth transistor, a control electrode for receiving a second input signal, and a second current electrode for providing the predetermined information; and

a sixth transistor having a first current electrode coupled to the second current electrode of the fifth transistor, a control electrode coupled to the output terminal of the second inverter, and a second current electrode coupled to the second supply voltage terminal.

11. The integrated circuit memory of claim 9, wherein the addressable fuse circuits are assigned as an N×

M bit fuse array, where N and M are integers, and the plurality of latch circuits receive M bits in parallel from a predetermined location of the addressable fuse circuits depending on the decoded address signal.

12. The integrated circuit memory of claim 11, wherein the N×

M bit fuse array is distributed around a periphery of the integrated circuit memory.

13. The integrated circuit memory of claim 9, wherein the latch circuit comprises a first input terminal coupled to the addressable fuse circuit for receiving the stored fuse information, a second input terminal for receiving a test data in signal, a third input terminal for receiving a test mode signal, a fourth input terminal for receiving a clock signal, and an output terminal for providing a scan out signal representative of one of the predetermined information or the test data in signal in response to the test mode signal.

14. An integrated circuit memory with redundancy, the integrated circuit memory implementing a boundary-scan test according to a Joint Test Action Group (JTAG) boundary-scan standard, comprising:

a plurality of memory cells organized in rows and columns;

a redundant column of memory cells for replacing a defective column of the plurality of memory cells;

a plurality fuse of circuits for storing redundancy information, the redundancy information for addressing the redundant column of memory cells when the redundant column of memory cells replaces the defective column of the plurality of memory cells; and

a plurality of serially connected latch circuits to form a scan chain, each latch circuit, coupled to a corresponding one of the fuse circuits for selectively providing the redundancy information when the integrated circuit memory is in a test mode.

15. The integrated circuit memory of claim 14, wherein a latch circuit of the plurality of latch circuits comprises a flip-flop circuit having a first input terminal coupled to the fuse circuit for receiving a portion of the redundancy information, a second input terminal for receiving a test data in signal, a third input terminal for receiving a test mode signal, a fourth input terminal for receiving a clock signal, and an output terminal for providing a scan out signal representative of one of the redundancy information or the test data in signal in response to the test mode signal.

16. The integrated circuit memory of claim 14, further comprising:

a shift register having an input terminal for receiving a shifted-in test data in signal, a plurality of serially connected registers, and a plurality of output terminals for providing an address signal;

a decoder circuit coupled to the shift register, for receiving the address signal, and in response, providing a decoded address signal;

wherein the plurality fuse circuits are an addressable fuse circuits for providing the redundancy information in response to the decoded address signal; and

wherein the plurality latch circuits are for receiving in parallel and serially shifting the redundancy information from the addressable fuse circuits, and for providing the shifted redundancy information in response to the integrated circuit memory being in the test mode.

17. The integrated circuit memory of claim 16, wherein the addressable fuse circuits are arranged as an N×

M bit fuse array, where N and M are integers, and the plurality of latch circuits receive M bits in parallel from a predetermined location of the addressable fuse circuits depending on the decoded address signal.

18. The integrated circuit memory of claim 17, wherein the N×

M bit fuse array is distributed around a periphery of the integrated circuit memory.