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Integrated circuit memory using fusible links in a scan chain

  • US 5,677,917 A
  • Filed: 04/29/1996
  • Issued: 10/14/1997
  • Est. Priority Date: 04/29/1996
  • Status: Expired due to Term
First Claim
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1. An integrated circuit memory implementing a scan test, comprising:

  • a plurality of fuse circuits for storing predetermined information concerning the integrated circuit memory; and

    a plurality of latch circuits, coupled to the plurality of fuse circuits, each fuse circuit of the plurality of fuse circuit coupled to a corresponding one of the plurality of latch circuits, the plurality of latch circuits serially coupled to form a scan chain for selectively providing the predetermined information when the integrated circuit memory is in a test mode.

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