Apparatus and method for a memory unit with a processor integrated therein

• US 5,678,021 A
• Filed: 10/17/1994
• Issued: 10/14/1997
• Est. Priority Date: 08/25/1992
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Poteet, Kenneth A., Neal, Joe H., Pawate, Basavaraj I.
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): BRAGDON, REGINALD GLENWOOD
• Application Number:
  US08/324,291
• Time in Patent Office: 1,093 Days
• Field of Search: 395/474, 395/477, 395/478, 395/479, 395/431, 395/293, 395/442, 395/200.05, 395/428
• US Class Current: 711/104
• CPC Class Codes: G06F 15/7821 Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory

Abstract

A smart memory (10) is provided that includes data storage (12 and 18) and a processing core (14 and 16) for executing instructions stored in the data storage area (12 and 18). Externally, smart memory (10) is directly accessible as a standard memory device. In a first mode of operation, the smart memory (10) is a data storage facility for an associated central processing unit (22). In a second mode of operation, the smart memory (10) is a storage facility for the processing core (14 and 16) and for central processing unit (22) for simultaneous execution of instructions. The central processing unit (22) controls the mode of operation and determines the instructions executed by the processing core (14 and 16). The wide data bus, available with an integrated processor/storage facility, permits certain processing operations to be off-loaded to the smart memory (10) where the processing operations can be performed more efficiently.

Claims

1. A smart memory for use with an external device, said smart memory storing data and instructions for processing by said external device, wherein a package including said smart memory has the same external lead configuration as a standard memory package, said smart memory comprising:

a storage unit, said storage unit coupled to said external device and functioning as a memory unit for said external device, said storage unit including;

a data memory, and

a program memory, said program memory storing instructions; and

a processor coupled to said external device and to said storage unit, said processor operating in response to control signals from said external device, said processor including;

an instruction decoder for decoding instructions stored in said program memory, and

a logic unit coupled to said instruction decoder, said logic unit processing data stored in said storage unit in response to decoded instructions, said data storage and processor integrated in a single integrated circuit, wherein said processor processes data in parallel with execution of instructions by said external device under control of said external device.

2. The smart memory of claim 1, wherein said processor switches between a smart mode and a standard mode in response to a control signal from said external device, said processor prevented from processing data in said standard mode.

3. The smart memory of claim 1, wherein said storage unit includes a specific memory location for storing mode information, said processor switching between a smart mode and a standard mode in response to mode information retrieved from said specific memory location by said processor, said processor prevented from processing data in said standard mode.

4. The smart memory of claim 1 further comprising a control signal lead coupling said external device and said processor, wherein said external device applies a control signal to said processor causing said processor to implement an interrupt task.

5. The smart memory of claim 1, wherein said storage unit includes a specific memory location for storing interrupt generate information, retrieval of said interrupt generate information in said specific memory location by said external device causing said processor to implement an interrupt task.

6. The smart memory of claim 1 further comprising a control signal lead coupling said external device and said processor, wherein said external device applies a signal to said processor over said control signal lead resulting in a resetting of said processor.

7. The smart memory of claim 1, wherein said storage unit includes a specific memory location for storing reset information by said external device, wherein said reset information retrieved from said specific location causes a resetting of said processor.

8. The smart memory of claim 1, wherein said storage unit includes a specific memory location for storing information causing said processor to start and stop executing instructions, retrieval of said information from said specific memory location by said processor controlling processing of data by said processor.

9. The smart memory of claim 1 further comprising a control signal lead coupling said external device and said processor, wherein said processor provides a signal to said external device indicating completion of a task by said processor.

10. The smart memory of claim 1, wherein said storage unit includes a task completed memory location for storage of task completed information therein by said processor, retrieval of task completed information from said task completed memory location indicating to said external device completion of a task by said processor.

11. A processing system comprising:

at least one external device, said at least one external device including a central processing unit; and

an integrated circuit, wherein a package including said integrated circuit has the same external lead configuration as a standard memory package, said integrated circuit including;

a memory unit functioning as memory for said at least one external device and having;

a data memory, and

a program memory, said program memory storing instructions;

a processor coupled to said memory unit and having;

an instruction decoder for retrieving and decoding instructions stored in said program memory; and

a logic unit coupled to said instruction decoder for processing signal groups stored in said data memory in accordance with decoded instructions;

a system bus coupling said memory unit and said at least one external device for exchanging instructions and data therebetween; and

at least one control signal lead extending between said at least one external device and said integrated circuit for connecting said at least one external device to said processor;

wherein said central processing unit and other external devices coupled to said system bus can directly access said memory during processing of signal groups by said processor.

12. The system of claim 11, wherein said central processing unit is operable to off load processing tasks to said integrated circuit for implementation by said processor.

13. The system of claim 11, wherein operation of said processor is halted during accesses to said integrated circuit by said central processing unit and by other external devices.

14. The system of claim 11 further comprising a bus arbitrator coupled to said system bus and operable to grant control of said system bus, and wherein said at least one control signal lead includes a bus request lead and a bus grant lead, said integrated circuit gaining control of said system bus by operation of said bus arbitrator.

15. A smart memory for use with an external device, wherein a package including said smart memory has the same external lead configuration as a standard memory package, said smart memory comprising:

a storage unit providing memory for said external device, said storage unit including;

a data memory storing signal groups, and

a program memory, said program memory storing instructions;

a processor connected to said storage unit;

said processor including;

an instruction decode unit for decoding said instructions, and

a logic unit coupled to said instruction decode unit for processing signal groups in said data memory in accordance with said instructions stored in said program memory, wherein said storage unit and said processor are integrated in a single integrated circuit; and

external leads providing apparatus for connecting said external device to said storage unit for an exchange of signal groups between said external device and said storage unit, wherein processing of signal groups by said processor is controlled by said external device.

16. The smart memory of claim 15 further including a control signal lead connecting said processor and said external device, wherein said external device provides a signal to said processor for switching said processor between a smart mode, wherein said processor and said external device process signal groups stored in said storage unit, and a standard mode, wherein only said external device processes signal groups from said storage unit.

17. The smart memory of claim 15, wherein said storage unit includes a specific memory location for storing mode information by said external device, retrieval of said mode information by said processor in said specific memory location resulting in a switching of said processor between a smart mode and a standard mode.

18. The smart memory of claim 15 further including a control signal lead connecting said processor and said external device, wherein said external device applies an interrupt signal to said processor causing said processor to implement an interrupt task.

19. The smart memory of claim 15, wherein said storage unit includes a specific memory location for storing interrupt generate information by said external device, retrieval of said interrupt generate information from said specific memory location by said processor causing said processor to implement an interrupt task.

20. The smart memory of claim 15 further including a control signal lead connecting said processor and said external device, wherein said external device applies a reset signal to said processor to reset said processor.

21. The smart memory of claim 15, wherein said storage unit includes a specific memory location for storing reset information by said external device, retrieval of said reset information from said specific memory location by said processor resetting said processor.

22. The smart memory of claim 15, wherein said storage unit includes a specific memory location for storing start and stop instruction information by said external device, retrieval of said start and stop instruction information from said specific memory location by said processor causing said processor to start and to stop executing instructions.

23. The smart memory of claim 15 further including a control signal lead connecting said processor and said external device, wherein said processor applies a task completed signal to said external device indicative of completion of a task by said processor.

24. The smart memory of claim 15, wherein said storage unit includes a task completed memory location for storing task complete information by said processor, retrieval of said task complete information from said task completed memory location by said external device indicating to said external device completion of a task by said processor.

25. A method of data processing by a processing device, said method comprising the steps of:

providing an external lead configuration of a package including an integrated circuit to be the same as an external lead configuration of a standard memory package, said integrated circuit having a memory unit and a processor;

storing instructions by said processing device in a program memory portion of said memory unit, said memory unit providing a memory for said processing device;

storing data from said processing device in a data memory portion of said memory unit; and

as a result of control signals from said processing device, causing said processor to decode instructions stored in said program memory portion of said integrated circuit and to process data stored in said data memory portion by said processor unit, processed data being stored in said data memory portion of said memory unit for retrieval by said processing device;

wherein data and instructions stored in said memory unit of said integrated circuit are accessible by said processing device, control signals from said processing device causing said integrated circuit to operate in a first mode wherein only said processing device processes data from said memory unit, control signals from said processing device causing said integrated circuit to operate in a second mode wherein both said processing device and said processor process data in said data memory portion.

26. A smart memory for use with central processing unit, said smart memory comprising:

a storage unit coupled to said central processing unit and providing a memory for said central processing unit, said data storage and said central processing unit exchanging signal groups therebetween, said storage unit including a program memory portion for storing processor instructions, wherein a package including said smart memory has the same external lead configuration as a standard memory package; and

a processor coupled to said storage unit, said storage unit and said processor exchanging signal groups therebetween, said processor including an instruction decoder for decoding instructions from said program memory portion, said smart memory having a first mode of operation in which said storage unit is accessible to said central processing unit for processing of signal groups, said smart memory having a second mode of operation wherein said storage unit is accessible to said central processing unit and to said processor for simultaneous signal group processing by said central processing unit and said processor, wherein said modes of operation are determined by control signals from said central processing unit.

27. The smart memory of claim 26 further including a memory control unit, said memory control unit preventing conflicts between said central processing unit and said processor resulting from simultaneous accesses to said storage unit, said central processing unit having priority in storage unit access conflicts.

28. The data processing unit of claim 26 wherein, in said second mode of operation, operation of said processor is suspended when said central processing unit accesses said storage unit.

29. A data processing system comprising:

a central processing unit; and

an integrated device coupled to said central processing unit, wherein a package including said integrated circuit device has the same external lead configuration as a standard memory package, said integrated device including;

a processor including a logic unit and an instruction decoder; and

a storage unit connected to said central processing unit and providing a memory for said central processing unit, said storage unit connected to said processor for exchanging signal groups stored in said storage unit, said storage unit including a program memory portion for storing instructions, said instructions being decoded by said instruction decoder and applied to said logic unit, said logic unit processing signal groups according to decoded instructions;

wherein said data processing system has two modes of operation, said central processing unit processing signal groups from said storage unit in a first mode of operation in response to control signals from said central processing unit, said processor and said central processing unit simultaneously processing signal groups from said data storage in response to control signals from said central processing unit in a second mode of operation.

30. For use in a data processing system having at least one connector for coupling memory modules to a processing unit, a smart memory module comprising:

an external lead configuration for attachment to said connector, wherein a package including said smart memory module has the same external lead configuration as a standard memory package;

a storage unit coupled to said external lead configuration, said processing unit interacting with said storage unit in the same manner as with a memory module, said data storage unit having a data memory for storing signal groups and a program memory for storing instructions; and

a processor connected to said storage unit for exchanging signal groups therebetween, said processor including an instruction decoder coupled to said program memory for retrieving and decoding instructions stored in said program memory, said processor including a logic unit responsive to decoded instructions for processing signal groups from said storage unit, operation of said processor controlled by control signals from said processing unit.

31. The smart memory of claim 30 wherein said smart memory module has a standard mode of operation in which only said processing unit interacts with said storage unit, said smart memory having a smart mode of wherein said processing unit and said processor interact with said data storage, said processing unit controlling which mode of operation is active by control signals.

32. The smart memory of claim 30 wherein said processing unit provides control signals to said processor by storing signal groups in selected memory locations.

33. The smart memory of claim 30 further including at least one control signal path between said processing unit and said processor for a transfer of control signals therebetween.

34. The smart memory of claim 30 wherein said processing unit has priority in accessing said storage unit.

35. The smart memory of claim 30 wherein said smart memory is implemented in an integrated circuit package.