Unbalanced FET mixer

• US 5,678,226 A
• Filed: 11/03/1994
• Issued: 10/14/1997
• Est. Priority Date: 11/03/1994
• Status: Expired due to Term

• Current Assignee: WJ Communications, Inc. (Qorvo, Inc.)
• Original Assignee: Watkins Johnson Co. (Qorvo, Inc.)
• Inventors: Li, Xiaohui, Vice, Michael Wendell
• Primary Examiner(s): Eisenzopf, Reinhard J.
• Assistant Examiner(s): LE, THANH C
• Application Number:
  US08/333,775
• Time in Patent Office: 1,076 Days
• Field of Search: 455/317, 455/318, 455/319, 455/323, 455/325, 455/327, 455/333, 327/113, 327/355, 327/356
• US Class Current: 455/333
• CPC Class Codes: H03D 7/125 with field effect transistors
• CPC Class Codes: H04B 1/28 the receiver comprising at least one semiconductor device having three or more electrodes

Abstract

A unbalanced mixer capable of operation in the absence of DC bias is disclosed herein. The mixer includes an input or local oscillator (LO) port for receiving an input signal. A first transistor has a control terminal coupled to the mixer input port, and an output terminal coupled to a first signal port of the mixer. The mixer further includes a resonator circuit, connected between the transistor control and output terminals, for providing signal isolation between the mixer input port and the first signal port. In a preferred implementation the resonator circuit comprises an inductive element in parallel with a first intrinsic capacitance of the transistor. The mixer may also include a diplexer circuit for coupling signal energy of a first frequency between the output terminal and the first signal port, and for coupling signal energy of a second frequency between the output terminal and a second signal port. A series resonant circuit, connected between the input or LO port and the transistor control terminal, may also be provided for amplifying the input signal. In a preferred implementation the series resonant circuit comprises an input inductive element and an input intrinsic capacitance of the first transistor.

Claims

1. A mixer, comprising:

an input port for receiving local oscillator (LO) input signal;

a first transistor having a gate, a drain, and a source terminal, said gate terminal coupled to said input port, and said drain terminal coupled to a radio frequency (RF) signal port and an intermediate frequency (IF) signal port;

a resonator circuit including an inductive element connected in parallel with a first intrinsic capacitance of said first transistor between said gate terminal and said drain terminal, said resonator circuit providing signal isolation between said LO input port and said RF signal port;

a diplexer circuit for coupling signal energy of a first frequency between said drain terminal and said RF signal port, and for coupling signal energy of a second frequency between said drain terminal and said IF signal port; and

a series resonant circuit connected to said LO input terminal, said series resonant circuit including and input inductive element and an input intrinsic capacitance of said first transistor.

2. The mixer of claim 1 further including a reverse-breakdown prevention circuit, connected with said series resonant circuit at said LO input port of said mixer, for preventing said input signal from causing reverse-breakdown at said gate terminal of said first transistor.

3. An unbalanced FET mixer, comprising:

a first FET transistor having a gate, a drain, and a source, said gate being coupled to a first LO port of said mixer;

a diplexer circuit interposed between said drain and said RF and IF ports of said mixer;

a resonator circuit connected between said gate and drain, comprising an inductive element in parallel with a first intrinsic gate-drain capacitance of said first FET transistor, said resonator circuit providing signal isolation between said LO and RF ports of said mixer; and

a series resonant circuit connected between said LO port and said gate of said first FET transistor, said series resonant circuit including an input inductive element and a gate-source intrinsic capacitance of said first FET transistor.

4. The mixer of claim 3 wherein said diplexer circuit further includes inductive and capacitive circuit elements for coupling signal energy of a first frequency between said drain and said RF port, and for coupling signal energy of a second frequency between said drain and said IF port.

5. The mixer of claim 3 further including a reverse-breakdown prevention circuit, connected to said LO input port of said mixer, for preventing an input signal applied to said input port from causing reverse-breakdown at said gate of said first FET transistor.

6. An unbalanced FET mixer, comprising:

a local oscillator (LO) port for receiving a local oscillator signal;

a first FET transistor having a gate, a drain and a source, said gate being coupled to said LO port;

a diplexer circuit interposed between said drain and radio frequency (RF) and intermediate frequency (IF) ports of said mixer;

said drain being coupled through said diplexer circuit to said RF and IF ports of said mixer;

a resonator circuit including an inductive element connected with a drain-gate capacitance of said transistor between said gate and drain, said resonator circuit providing signal isolation between said RF and LO ports of said mixer; and

a series resonant circuit connected between sail LO port and said gate of said FET transistor, said series resonant circuit being resonant at a frequency of said local oscillator signal.

7. A mixer comprising:

an input port for receiving local oscillator CLO) input signal;

a first FET transistor having a gate, a drain, and a source terminal, said gate terminal coupled to said input port, and said drain terminal coupled to a radio frequency (RF) signal port and an intermediate frequency (IF) signal port;

a resonator circuit including a series combination of an inductor connected in series with a blocking capacitor and said combination connected in parallel with a first intrinsic capacitance of said first transistor between said gate terminal and said drain terminal, said blocking capacitor providing isolation between signals appearing at said IF port and said gate terminal, said resonator circuit providing signal isolation between said LO input port and said RF signal port;

a diplexer circuit for coupling signal energy of a first frequency between said drain terminal and said RF signal port, and for coupling signal energy of a second frequency between said drain terminal and said IF signal port;

a series resonant circuit connected to said LO input terminal, said series resonant circuit including an input inductive element and an input intrinsic capacitance of said first transistor; and

a reverse-breakdown prevention circuit, connected to said LO input port of said mixer, for preventing said input signal from causing reverse-breakdown at said LO input terminal of said first transistor.