FET with gate spacer

• US 5,679,589 A
• Filed: 04/03/1992
• Issued: 10/21/1997
• Est. Priority Date: 10/17/1989
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Lu, Chih-Yuan, Lee, Kuo-Hua, Sung, Janmye
• Primary Examiner(s): WILCZEWSKI, MARY A
• Application Number:
  US07/866,942
• Time in Patent Office: 2,027 Days
• Field of Search: 437/27, 437/28, 437/29, 437/30, 437/34, 437/40, 437/41, 437/44, 437/56, 437/57, 437/186, 437/192, 437/196, 437/200, 437/235, 437/238, 437/239, 437/241, 357/23.3, 357/23.4
• US Class Current: 438/305
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A semiconductor integrated circuit structure and method of fabrication is disclosed. The structure includes a FET gate with adjacent double or triple layered gate spacers. The spacers permit precise tailoring of lightly doped drain junction profiles having deep and shallow junction portions. In addition, a self-aligned silicide may be formed solely over the deep junction portion thus producing a reliable low contact resistance connection to source and drain.

Claims

1. A method of semiconductor integrated circuit fabrication comprising:

forming a gate stack over a substrate, said gate having a first overlying nitride layer;

forming a first oxide layer upon said gate stack and selected portions of said substrate;

depositing a second layer of nitride upon said first oxide layer;

depositing a second oxide layer upon said second nitride layer;

etching said second oxide layer to form a first spacer;

etching said second nitride layer to form a second spacer underlying said first spacer;

said first nitride layer remaining upon said gate stack.

2. The method of claim 1 further including the steps of forming at least two junctions in said substrate;

depositing a conductive material upon said substrate and upon at least one gate stack, said gate stack having said first nitride layer upon it, said conductive material contacting both of said junctions;

patterning said conductive material.

3. The method of claim 2 wherein said conductive material is chosen from the group consisting of polysilicon, aluminum, tungsten, titanium, tantalum, metal silicide, or molybdenum.

4. The method of claim 1 which said step of forming a gate stack includes:

growing an oxide layer upon said substrate;

depositing a polysilicon layer on said oxide layer;

depositing a nitride layer upon said polysilicon layer; and

etching said oxide layer, said polysilicon layer, and said nitride layer to form said gate stack having an overlying nitride layer.