Method of making raised-bitline contactless trenched flash memory cell
First Claim
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1. A method of manufacture of a raised-bitline, contactless flash memory device with trenches comprising the steps as follows:
- forming a semiconductor substrate doped with a first conductivity type, and a first well of an opposite conductivity type therein,forming over said first well a second well of said first conductivity type,forming trenches extending through said second well into said first well,filling said trenches with a first dielectric layer,forming a gate oxide layer over said second well,forming a first doped polysilicon layer over said gate oxide layer,patterning said first doped polysilicon layer,forming an interpolysilicon dielectric layer over said doped first polysilicon layer,forming a second doped polysilicon layer over said interpolysilicon dielectric layer,forming a dielectric cap over said second doped polysilicon layer,masking and etching said dielectric cap, second doped polysilicon, interpolysilicon dielectric, first doped polysilicon, and gate oxide layers to form gate electrode stacks for said flash memory device,forming spacer dielectric structures adjacent to the sidewalls of said stacks,forming source/drain regions in said second well self-aligned with said spacer dielectric structures,forming a third doped polysilicon layer over said stacks and said source regions and said drain regions, andetching back said third doped polysilicon layer to form raised bitlines from said third doped polysilicon layer over said source/drain regions by etching back said third doped polysilicon layer.
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Abstract
A raised-bitline, contactless flash memory device with trenches on a semiconductor substrate doped with a first conductivity type includes a first well of an opposite conductivity type comprising a deep conductor line to a device, and a second well of the first conductivity type above the first well comprising a body line to the device. Deep trenches extend through the second well into the first well. The trenches are filled with a first dielectric. There are gate electrode stacks for a flash memory device including a gate oxide layer over the device. First doped polysilicon floating gates are formed over the gate oxide layer. An interpolysilicon dielectric layer is formed over floating gate electrodes, and control gate electrodes formed of doped polysilicon layer overlie the interpolysilicon dielectric layer. A dielectric cap overlies the control gate electrodes. Source/drain regions are formed in the second well self-aligned with the stacks as well as spacer dielectric structures formed adjacent to the sidewalls of the stacks. A third doped polysilicon layer patterned into raised bitlines overlies source/drain regions.
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Citations
15 Claims
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1. A method of manufacture of a raised-bitline, contactless flash memory device with trenches comprising the steps as follows:
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forming a semiconductor substrate doped with a first conductivity type, and a first well of an opposite conductivity type therein, forming over said first well a second well of said first conductivity type, forming trenches extending through said second well into said first well, filling said trenches with a first dielectric layer, forming a gate oxide layer over said second well, forming a first doped polysilicon layer over said gate oxide layer, patterning said first doped polysilicon layer, forming an interpolysilicon dielectric layer over said doped first polysilicon layer, forming a second doped polysilicon layer over said interpolysilicon dielectric layer, forming a dielectric cap over said second doped polysilicon layer, masking and etching said dielectric cap, second doped polysilicon, interpolysilicon dielectric, first doped polysilicon, and gate oxide layers to form gate electrode stacks for said flash memory device, forming spacer dielectric structures adjacent to the sidewalls of said stacks, forming source/drain regions in said second well self-aligned with said spacer dielectric structures, forming a third doped polysilicon layer over said stacks and said source regions and said drain regions, and etching back said third doped polysilicon layer to form raised bitlines from said third doped polysilicon layer over said source/drain regions by etching back said third doped polysilicon layer. - View Dependent Claims (2, 3, 4, 5, 6, 10, 11, 12, 13, 14)
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7. A method of manufacture of a raised-bitline, contactless flash memory device with trenches comprising the steps as follows:
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forming a semiconductor substrate doped with a first P- conductivity type, and a first well of an opposite N-conductivity type therein, forming over said first well a second well of said first P-conductivity type, forming trenches extending through said second well into said first well, filling said trenches with a first dielectric, forming a gate oxide layer over said second well, forming a first doped polysilicon layer over said gate oxide layer, patterning said first doped polysilicon layer, forming an interpolysilicon dielectric layer over said doped first polysilicon layer, forming a second doped polysilicon layer over said interpolysilicon dielectric layer, forming a dielectric cap over said second doped polysilicon layer, masking and etching said dielectric cap, second doped polysilicon, interpolysilicon dielectric, first doped polysilicon, and gate oxide layers to form gate electrode stacks for said flash memory device, forming spacer dielectric structures adjacent to the sidewalls of said stacks, forming source/drain regions in said second well self-aligned with said stacks, forming a third doped polysilicon layer over said stacks, and forming raised bitlines from said third doped polysilicon layer over said source/drain regions by etching back said third doped polysilicon layer. - View Dependent Claims (8, 9)
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15. A method of manufacture of a raised-bitline, contactless flash memory device with trenches comprising the steps as follows:
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forming a semiconductor substrate doped with a first P- conductivity type, and a first well of an opposite N- conductivity type therein, forming over said first well a second well of said first P- conductivity type, forming trenches with a depth of from about 8 μ
m to about 10 μ
m and a width from about 0.3 μ
m to about 0.5 μ
m extending through said second well into said first well,filling said trenches with a blanket, first dielectric layer comprising a BPSG glass layer formed by a chemical vapor deposition process with a thickness of from about 10 μ
m to about 12 μ
m, said BPSG glass layer being silicon glass composed of boron (B) from about 1% to about 12% and phosphorous (P) from about 4% to about 6%,heating said device to reflow said first dielectric layer at a temperature of from about 850°
C. to about 950°
C. to planarize said BPSG glass layer, followed by a reactive ion etching etchback process to remove from about 10 μ
m to about 12 μ
m of said first dielectric layer above the surface of said second well,forming a gate oxide layer over said device having a thickness from about 80 Å and
about 90 Å
,forming a first doped polysilicon layer over said gate oxide layer having a thickness from about 1,500 Å and
about 1,800 Å
,patterning said first doped polysilicon layer, forming an interpolysilicon dielectric layer comprising an oxide/nitride/oxide layer comprising a thermally formed silicon oxide layer having a thickness of from about 60 Å
to about 80 Å
, a silicon nitride layer having a thickness of from about 80 Å
to about 100 Å
, and another thermally formed silicon oxide layer having a thickness from about 60 Å
to about 80 Å
,forming a second doped polysilicon layer over said interpolysilicon dielectric layer having a thickness from about 1,500 Å and
about 2,000 Å
,forming a polycide layer composed of tungsten silicide over said second doped polysilicon layer having a thickness from about 100 Å and
about 180 Å
,forming dielectric cap layers over said polycide layer, said dielectric cap layers comprising a blanket pad oxide layer composed of silicon dioxide from about 200 Å
to about 400 Å
thick and a blanket silicon nitride layer from about 800 Å
to about 1,000 Å
thick, masking and etching said dielectric cap, second doped-polysilicon, interpolysilicon dielectric, first doped polysilicon, and gate oxide layers to form gate electrode stacks for said flash memory device with said cap layers on top,forming N- lightly doped source/drain regions in said second well self-aligned with said gate electrode stacks with a dopant dose from about 5E13 ions/cm2 to about 5E14 ions/cm2 by the process of ion implantation at an energy from about 30 keV to about 40 keV, forming spacer dielectric structures adjacent to the sidewalls of said stacks, forming source/drain regions in said second well which are self-aligned with said spacer dielectric structures with a dopant dose from about 1E15 ions/cm2 to about 5E15 ions/cm2 by the process of ion implantation at an energy from about 40 keV to about 50 keV, forming a third doped polysilicon layer over said stacks including said source regions and said drain regions having a thickness between about 2 μ
m and about 3 μ
m, andetching back said third doped polysilicon layer to form raised bitlines from said third doped polysilicon layer over said source/drain regions by etching back said third doped polysilicon layer having a thickness between about 0.2 μ
m and about 0.3 μ
m.
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Current AssigneeTaiwan Semiconductor Manufacturing Company Limited
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Original AssigneeTaiwan Semiconductor Manufacturing Company Limited
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InventorsLiang, Mong-Song, Lin, Ruei-Ling, Hsu, Ching-Hsiang
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Primary Examiner(s)Niebling, John
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Assistant Examiner(s)Booth, Richard A.
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Application NumberUS08/766,079Time in Patent Office309 DaysField of Search437/43, 437/52, 437/67US Class Current438/257CPC Class CodesH10B 41/30 characterised by the memory...H10B 69/00 Erasable-and-programmable R...
