Portable electronic module having EPROM memory, systems and processes

• US 5,679,944 A
• Filed: 11/18/1994
• Issued: 10/21/1997
• Est. Priority Date: 06/15/1994
• Status: Expired due to Term

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Dallas Semiconductor Corporation (Analog Devices, Inc.)
• Inventors: Cusey, James P., Harrington, Bradley M.
• Primary Examiner(s): Hajec, Donald T.
• Assistant Examiner(s): Le, Thien Minh
• Application Number:
  US08/342,068
• Time in Patent Office: 1,068 Days
• Field of Search: 235/930, 235/362, 235/384, 235/441, 235/492, 235/487
• US Class Current: 235/492
• CPC Class Codes: G06K 19/07 with integrated circuit chips

Abstract

A circuit positioned in a substantially token-shaped body, the circuit that comprises (a) a serial port to receive and transmit information following a write signal, a read signal, and a program signal; (b) a scratchpad memory coupled to the serial port to hold information that is received or transmitted; (c) an electrically programmable memory coupled to the scratchpad memory; (d) program port to receive program information and program the electrically programmable memory, said program port deriving all voltages necessary to program said electrically programmable memory from said program signal; and (e) control logic coupled to the serial port and the scratchpad memory and the electrically programmable memory, the control logic transfers information to and from the scratchpad memory to the electrically programmable memory as a block pursuant to a block transfer command received at the serial port. The memory subsections comprise a block of memory that can redirects data requests to other locations in the memory subsections and can be write protected by protecting information found in the block and/or by preventing the block from being redirected.

Claims

1. A circuit positioned in a substantially token-shaped body, said substantially token-shaped body having at least one conductive surface, said circuit comprising:

(a) a serial port electrically coupled to said at least one conductive surface of said substantially token-shaped body to receive and transmit information, said information following a write signal, a read signal, and a program signal;

(b) a scratchpad memory coupled to said serial port to hold information that is received or transmitted by said serial port;

(c) an electrically programmable memory coupled to said scratchpad memory to house said information received by said serial port;

(d) program port electrically coupled to said at least one conductive surface of said substantially token-shaped body to receive program information following said program signal to program said electrically programmable memory, said program port deriving all voltages necessary to program said electrically programmable memory from s program signal; and

(e) control logic coupled to said serial port and said scratchpad memory and said electrically programmable memory, said control logic transfers information to and from said scratchpad memory to said electrically programmable memory as a block pursuant to a block transfer command received at said serial port.

2. The memory of claim 1, wherein said electronic token has a first electrically conductive surface and a second electrically conductive surface that combine to create a hollow cavity, said serial port, said scratchpad memory, said program port, said electrically programmable memory, and said control logic positioned inside said hollow cavity, said first conductive surface and said second conductive surface can be electrically coupled to transmit electrical signals generated by said serial port, said scratchpad memory, said program port, said electrically programmable memory, and control logic and to receive externally generated electrical signals.

3. The circuit of claim 2, wherein:

(a) said first electrically conductive surface and said second electrically conductive surface are planar.

4. The circuit of claim 1, wherein:

(a) said control logic allows access to a generated cyclic redundancy check value.

5. The circuit of claim 1, wherein said block is equal to 8 bits or more.

6. The circuit of claim 1, wherein said electrically programmable memory is divided into a plurality of memory subsections, all of which are coupled to said scratchpad memory and said control logic;

said control logic transfers information to and from said scratchpad memory to said plurality of memory subsections of said electrically programmable memory as a block pursuant to a block transfer command received at said serial port.

7. The circuit of claim 6, wherein at least four memory subsections comprise said plurality of memory.

8. The circuit of claim 2, wherein said serial port, said scratchpad memory, said electrically programmable memory and said control logic is powered by voltage intermittently applied between said first and second electrically conductive surface areas.

9. The circuit of claim 2, further comprising a capacitor for storing energy from said voltage intermittently applied between said first and second electrically conductive surface areas.

10. The circuit of claim 2, wherein:

(a) skid first electrically conductive surface comprises a first flat face; and

(b) said second electrically conductive surface comprises

(b1) a second flat face parallel to said first flat face; and

(b2) a portion of a first electrically conductive surface which is approximately perpendicular to said first flat face and said second flat face.

11. The circuit of claim 6, further comprising:

(g) a voltage level detector coupled to a first and a second surface of said at least one conductive surface for receiving signals applied as voltage level differences between said first and said second conductive surfaces; and

(h) a switch connecting said first and said second conductive surfaces for sending signals by changing a resistance between said first and said second conductive surfaces.

12. The circuit of claim 11, wherein said voltage level differences are approximately 5 volts, said voltage level differences created by a first voltage level and a second voltage level, said first and second voltage levels correspond to a logical high and a logical low.

13. The circuit of claim 1, wherein said substantially token-shaped body is button-shaped and has a flange extending from a perimeter of said substantially token-shaped body.

14. The circuit of claim 6, wherein said serial port, said scratchpad memory, said electrically programmable memory and said control logic is integrated on a monolithic piece of silicon.

15. The circuit of claim 1, wherein said substantially token-shaped body is mountable to a physical item.

16. The circuit of claim 15, wherein said item is selected from the group consisting of maintenance records, retail products, machinery, cards, personnel identification badges, machinery, access control devices, and a currency equivalent device.

17. The circuit of claim 2, wherein substantially token-shaped body has only said first and second electrically conductive surface.

18. The circuit of claim 1, wherein said serial port, said scratchpad memory, said electrically programmable memory and said control logic is packaged in a low-height package.

19. The circuit of claim 18, wherein said low-height package is at least one of a flat pack and a small outline integrated circuit.

20. The circuit of claim 1, wherein said serial port, said scratchpad memory, said electrically programmable memory and said control logic is combined into an integrated circuit that is mounted on a very small printed circuit board.

21. The circuit of claim 1, wherein said substantially token-shaped body is approximately 6 mm in diameter and approximately 3 mm thick.

22. The circuit of claim 1, wherein said substantially token-shaped body is comprised of metal.

23. The circuit of claim 1, wherein said program port and write signal, and said program signal corresponding to receiving and transmitting information are multiplexed together on a single data line.

24. The circuit of claim 6, wherein said scratchpad memory has a first size android electrically programmable memory has a second size.

25. The circuit of claim 24, wherein said second size is approximately equal to 16,384 bits.

26. The circuit of claim 1, wherein a bus master module is coupled to said serial port and controls communication to and from said serial port.

27. The circuit of claim 26, wherein said bus master module holds a data line to a first voltage level for a first time period, creates a transition between said first voltage level and a second voltage level, holds the data line at said second voltage level for a second time period;

and then samples said data line to determine whether a data value is a first data value or a second data value at a first sample time.

28. The circuit of claim 27, wherein said first time period is at least one microsecond.

29. The circuit of claim 27, wherein said first voltage level corresponds to a logic high level and is selected from the group consisting of approximately 3 volts and approximately 5 volts.

30. The circuit of claim 27, wherein said second voltage level is approximately ground and corresponds to a logic low level.

31. The circuit of claim 27, wherein said second time period is at least one microsecond.

32. The circuit of claim 27, wherein said first sample time is at least 30 microseconds from said transition.

33. The circuit of claim 27, wherein said master bus module holds a data line coupled to said serial port via a first electrically conductive surface to a first voltage level for a first time period, creates a transition between said first voltage level and a second voltage level, holds said first data line to said second voltage level for a second time period, and samples said data line by said master bus module to determine whether a data value is a first data value or a second data value at a first time.

34. The circuit of claim 6, further comprising:

(g) a voltage level detector coupled a first and a second surface of said at least one conductive surface for receiving signals applied as voltage level differences between said first and said second conductive surfaces.

35. The circuit of claim 1, wherein said electrically programmable memory comprises at least one memory cell, each memory cell comprising a first transistor having a gate, source and drain, said circuit further comprising a voltage clamping circuit that directs and adjusts a first voltage and a second voltage to said gate and said drain, both of which have been derived from a program voltage received hybrid program port, said first voltage and said second voltages are substantially independent of operating temperature and said first voltage and said second voltage are substantially independent from one another.

36. The circuit of claim 1, wherein said serial port and said program port are combined into a single port.

37. The circuit of claim 1, wherein said serial port comprises a voltage switch circuit detects voltage differences received at said serial port and interprets said voltage difference to determine whether it should be directed to reading said electrically programmable memory or to program said electrically programmable memory.

38. The circuit of claim 37, wherein if said voltage switch determines said voltage difference should be used to program said electrically programmable memory, said voltage switch activates circuitry to adjust said voltage difference to run other circuitry comprised in said circuit.

39. The circuit of claim 6, wherein said memory subsections comprise a block of memory, said block of memory redirects data requests to other locations in said memory subsections, said block can be write protected.

40. The circuit of claim 39, wherein said block is write protected by protecting information found in said block and/or by preventing said block from being redirected.

41. The circuit of claim 1, wherein said electrically programmable memory comprises blocks of memory to redirect data requests to other locations in said electrically programmable memory.

42. The circuit of claim 1, wherein said electrically programmable memory is also read only memory.

43. The circuit of claim 1, further comprising:

(g) a protection circuit to protect said scratchpad memory, said electrically programmable memory coupled to said scratchpad memory, and said control logic from electrostatic discharge.