Semiconductor tunnel junction with enhancement layer

• US 5,679,963 A
• Filed: 12/05/1995
• Issued: 10/21/1997
• Est. Priority Date: 12/05/1995
• Status: Expired due to Term

• Current Assignee: Sandia Corporation (Martin Marietta Corporation)
• Original Assignee: Sandia Corporation (Martin Marietta Corporation)
• Inventors: Klem, John F., Zolper, John C.
• Primary Examiner(s): FAHMY, WAEL M
• Application Number:
  US08/567,678
• Time in Patent Office: 686 Days
• Field of Search: 257/184, 257/46, 257/94, 257/96, 257/97, 257/183, 136/249, 136/252
• US Class Current: 257/46
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/88 Tunnel-effect diodes
• CPC Class Codes: H01L 31/06 characterised by potential barriers
• CPC Class Codes: H01L 31/0693 the devices including, apart from doping material or other impurities, only AIIIBV compounds, e.g. GaAs or InP solar cells
• CPC Class Codes: H01L 31/0735 comprising only AIIIBV compound semiconductors, e.g. GaAs/AlGaAs or InP/GaInAs solar cells
• CPC Class Codes: H01L 33/0016 having at least two p-n junctions
• CPC Class Codes: H01L 33/0025 comprising only AIIIBV compounds
• CPC Class Codes: H01S 5/3095 Tunnel junction
• CPC Class Codes: Y02E 10/544 Solar cells from Group III-V materials

Abstract

The incorporation of a pseudomorphic GaAsSb layer in a runnel diode structure affords a new degree of freedom in designing runnel junctions for p-n junction device interconnects. Previously only doping levels could be varied to control the tunneling properties. This invention uses the valence band alignment band of the GaAsSb with respect to the surrounding materials to greatly relax the doping requirements for tunneling.

Claims

1. A tunnel junction semiconductor device consisting of:

a first layer of p-doped first semiconductor material, said material being either a group III-V or group II-VI alloy;

a second layer of n-doped second semiconductor alloy; and

a thin enhancement layer of p-doped third semiconductor alloy adjacent and between said first and second layers, said enhancement layer having a higher energy valence band than said first layer for reducing tunneling distance across the device;

said second layer and said enhancement layer materials being of the same class as the first layer.

2. The semiconductor device of claim 1 wherein each of said layers each consist of III-V alloys.

3. The semiconductor device of claim 2 wherein said enhancement layer is a layer of GaAs_1-y Sb_y, where 0<

y≦

1.

4. The semiconductor device of claim 3 wherein the level of doping of said first and second alloys is too low to support tunneling current between said alloys when said enhancement layer is not present.

5. The semiconductor device of claim 3, wherein said first and second alloys are one of the group consisting of:

InAlAs;

InGaAs;

AlGaAs; and

GaAs.

6. The semiconductor device of claim 3 wherein the percentage of GaSb in said GaAsSb enhancement layer is between approximately 49 and 65%.

7. A tandem semiconductor structure having first and second semiconductor devices connected in series by a thin tunnel current enhancement layer adjacent and between said devices,

a portion of said first device adjacent said enhancement layer consisting of a first layer of p-doped semiconductor alloy, and

a portion of said second device adjacent said enhancement layer consisting of a second layer of n-doped semiconductor alloy, and

said enhancement layer comprising a thin layer of semiconductor alloy having a different composition than each of said first and second layers, said enhancement layer being p-doped and having a higher energy valence band than said first layer for reducing tunneling distance across the first and second layers.

8. The semiconductor structure of claim 7 wherein said first and second layers each consist of first and second III-V alloys, respectively.

9. The semiconductor structure of claim 8 wherein said enhancement layer is a layer of GaAs_1-y Sb_y, where 0<

y≦

1.

10. The semiconductor structure of claim 9 wherein the level of doping of said first and second alloys is too low to support tunneling current between said alloys when said enhancement layer is not present.

11. The semiconductor structure of claim 9 wherein the enhancement layer is at least an order of magnitude thinner than each of said first and second alloys.

12. The semiconductor structure of claim 8, wherein said first and second alloys are one of the group consisting of:

InAlAs;

InGaAs;

AlGaAs; and

GaAs.

13. The semiconductor structure of claim 12 wherein said devices are solar cells.

14. The semiconductor structure of claim 12 wherein said devices are light emitting diodes.