Depleted base transistor with high forward voltage blocking capability

• US 5,679,966 A
• Filed: 10/05/1995
• Issued: 10/21/1997
• Est. Priority Date: 10/05/1995
• Status: Expired due to Term

• Current Assignee: Intellectual Ventures Holding 81 LLC (Intellectual Ventures LLC)
• Original Assignee: North Carolina State University (University of North Carolina System)
• Inventors: Thapar, Naresh I., Baliga, Bantval Jayant
• Primary Examiner(s): FAHMY, WAEL M
• Application Number:
  US08/539,748
• Time in Patent Office: 747 Days
• Field of Search: 257/139, 257/144, 257/330, 257/331, 257/332, 257/341, 257/342, 257/77
• US Class Current: 257/139
• CPC Class Codes: H01L 29/7391 Gated diode structures
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

A depleted base transistor with high forward voltage blocking capability includes cathode and anode regions on opposite faces of a semiconductor substrate, a base region therebetween, a rectifying junction for depleting a portion of the base region of majority free carriers and an insulated gate electrode in a trench for modulating the conductivity of the depleted portion of the base region. The regions are formed as a vertical stack of semiconductor layers with the anode region (e.g., P+) as the bottom layer, the buffer region (e.g., N+) on the anode region, the drift region/e.g., N-) on the buffer region, the blocking voltage enhancement region (e.g., N-) on the drift region and the cathode region (e.g., N+) as the top layer on the blocking voltage enhancement region. The trench extends into the substrate at the first face so that a sidewall thereof extends adjacent the cathode region and the blocking voltage enhancement region and defines an interface between these adjacent regions and the interior of the trench which contains the insulated gate electrode. The rectifying junction is provided to deplete at least a portion of the blocking voltage enhancement region so that the P-N diode formed by the stack of anode, buffer, drift, blocking voltage enhancement and cathode regions blocks forward voltages when the insulated gate electrode is maintained at the same potential as the cathode region.

Claims

1. A depleted base transistor comprising:

a semiconductor substrate having first and second opposing faces;

a cathode contact on the first face;

an anode contact on the second face;

a cathode region of first conductivity type in said substrate at the first face, said cathode region forming an ohmic contact with said cathode contact;

a trench in said substrate at the first face, said trench having a trench bottom and a trench sidewall extending between the trench bottom and the first face;

a base region of first conductivity type in said substrate, between said cathode region and said anode contact, said base region comprising;

a drift region of first conductivity type having a drift region doping concentration;

a blocking voltage enhancement region of first conductivity type extending between said drift region and said cathode region, said blocking voltage enhancement region forming non-rectifying junctions with said cathode region and said drift region and having a blocking voltage enhancement region doping concentration below the drift region doping concentration;

an insulated gate electrode in said trench; and

means, comprising a rectifying junction in said substrate, for depleting said blocking voltage enhancement region of majority free carriers to thereby inhibit traversal of majority carriers from said cathode region to said drift region.

2. The depleted base transistor of claim 1, further comprising an anode region of second conductivity type in said substrate at the second face, said anode region forming an ohmic contact with said anode contact and a P-N rectifying junction with said base region.

3. The depleted base transistor of claim 1, wherein the blocking voltage enhancement region doping concentration is less than about one half times the drift region doping concentration.

4. The depleted base transistor of claim 1, wherein said base region is of N-type conductivity and wherein said insulated gate electrode comprises polycrystalline silicon of P-type conductivity.

5. The depleted base transistor of claim 1, wherein said semiconductor substrate comprises monocrystalline silicon carbide.

6. The depleted base transistor of claim 2, wherein the trench sidewall defines an interface between said blocking voltage enhancement region and said insulated gate electrode.

7. The depleted base transistor of claim 6, wherein the trench bottom defines an interface between said drift region and said insulated gate electrode.

8. The depleted base transistor of claim 7, wherein a portion of the trench sidewall, adjacent the trench bottom, defines an interface between said drift region and said insulated gate electrode.

9. The depleted base transistor of claim 8, wherein the rectifying junction is selected from the group consisting of P-N and Schottky junctions.

10. The depleted base transistor of claim 7, wherein said base region further comprises a buffer region of first conductivity type between said drift region and said anode region and wherein said buffer region forms a non-rectifying junction with said drift region and a P-N junction with said anode region.

11. The depleted base transistor of claim 8, wherein said blocking voltage enhancement region extends between the trench sidewall and the rectifying junction.

12. The depleted base transistor of claim 11, wherein the rectifying junction comprises a collector region of second conductivity type on said blocking voltage enhancement region and wherein said collector region ohmically contacts said cathode contact.

13. A depleted base transistor comprising:

a monocrystalline silicon carbide substrate;

a cathode contact and an anode contact on said silicon carbide substrate;

a silicon carbide cathode region of first conductivity type in said silicon carbide substrate, said silicon carbide cathode region forming an ohmic contact with said cathode contact;

a silicon carbide anode region of second conductivity type in said silicon carbide substrate, said silicon carbide anode region forming an ohmic contact with said anode contact;

a silicon carbide base region of first conductivity type in said substrate, between said silicon carbide cathode region and said silicon carbide anode region, said silicon carbide base region comprising;

a silicon carbide drift region of first conductivity type having a drift region doping concentration;

a silicon carbide blocking voltage enhancement region of first conductivity type extending between said silicon carbide drift region and said silicon carbide cathode region, said silicon carbide blocking voltage enhancement region forming non-rectifying junctions with said silicon carbide cathode region and said silicon carbide drift region and having a blocking voltage enhancement region doping concentration below the drift region doping concentration;

a trench in said substrate at the first face, said trench having a trench bottom which defines an interface between said silicon carbide drift region and an interior of said trench and a trench sidewall which defines an interface between said silicon carbide blocking voltage enhancement region and the interior of said trench;

an insulated gate electrode in the interior of said trench; and

means, comprising a silicon carbide rectifying junction spaced from the trench sidewall and selected from the group consisting of P-N junctions and Schottky junctions, for depleting said silicon carbide blocking voltage enhancement region of majority free carriers to thereby inhibit traversal of majority carriers from said silicon carbide cathode region to said silicon carbide drift region.

14. The depleted base transistor of claim 13, wherein the silicon carbide blocking voltage enhancement region doping concentration is less than about one half times the silicon carbide drift region doping concentration.

15. The depleted base transistor of claim 13, wherein said silicon carbide base region is of N-type conductivity and wherein said insulated gate electrode comprises polycrystalline silicon of P-type conductivity.

16. The depleted base transistor of claim 13, wherein the silicon carbide rectifying junction comprises a silicon carbide collector region of second conductivity type in said silicon carbide substrate and wherein said silicon carbide collector region forms a P-N junction with said silicon carbide blocking voltage enhancement region and a P-N junction with said silicon carbide cathode region.

17. The depleted base transistor of claim 13, wherein the silicon carbide rectifying junction comprises a metal-filled trench having a bottom which defines an interface between a Schottky barrier metal and said silicon carbide blocking voltage enhancement region.

18. The depleted base transistor of claim 17, wherein the metal work function of the Schottky barrier metal is selected to fully deplete said silicon carbide blocking voltage enhancement region of majority free carriers when said insulated gate electrode, said cathode contact and said anode contact are biased to the same potential.

19. A trench-gated depleted base transistor, comprising:

a semiconductor substrate having a cathode contact and an anode contact thereon;

a cathode region of first conductivity type in said substrate and forming an ohmic contact with said cathode contact;

an anode region of second conductivity type in said substrate and forming an ohmic contact with said anode contact;

a base region of first conductivity type in said substrate, said base region forming non-rectifying and rectifying junctions with said cathode region and said anode region, respectively, and including a drift region having a nonuniform doping profile which is monotonically decreasing in a direction from said anode region to said cathode region;

a trench in said substrate, said trench having a trench sidewall which defines an interface between said nonuniformly doped drift region and an interior of said trench;

an insulated gate electrode in the interior of said trench; and

means, comprising a rectifying junction spaced from the trench sidewall, for depleting said nonuniformly doped drift region of majority free carriers to thereby inhibit traversal of majority carriers from said cathode region to said anode region when said anode region is forward biased relative to said cathode region.

20. The depleted base transistor of claim 19, wherein said base region comprises a buffer region of first conductivity type which forms an abrupt P-N junction with said anode region.

21. The depleted base transistor of claim 19, wherein said base region comprises a buffer region of first conductivity type which forms abrupt junctions with said anode region and said nonuniformly doped drift region.

22. The depleted base transistor of claim 19, wherein said base region is of N-type conductivity and wherein said insulated gate electrode comprises polycrystalline silicon of P-type conductivity.

23. The depleted base transistor of claim 19, wherein the rectifying junction comprises a collector region of second conductivity type in said nonuniformly doped drift region and wherein said collector region ohmically contacts said cathode contact.

24. A depleted base transistor comprising:

a semiconductor substrate having first and second opposing faces;

a cathode contact on the first face;

an anode contact on the second face;

an anode region, buffer region, drift region, blocking voltage enhancement region, cathode region and collector region in said substrate, said anode region, buffer region, drift region, blocking voltage enhancement region and cathode region being arranged to respectively form a P+N+N-N-N+ diode from said anode contact to said cathode contact, said anode region, buffer region, drift region, blocking voltage enhancement region and collector region being arranged respectively to form a P+N+N-N-P+ bipolar junction transistor from said anode contact to said cathode contact and wherein an N-type conductivity of said blocking voltage enhancement region is less than about one half times an N-type conductivity type of said drift region;

a trench in said substrate at the first face, said trench having a trench bottom and a trench sidewall extending between the trench bottom and the first face and adjacent the blocking voltage enhancement region; and

an insulated gate electrode in said trench and positioned relative to said blocking voltage enhancement region so that the application of a bias to said insulated gate electrode causes the formation of an accumulation layer of majority free carriers adjacent the trench sidewall, between said cathode region and said drift region.

25. The depleted base transistor of claim 24, wherein said anode region, buffer region, drift region, blocking voltage enhancement region, cathode region and collector region form abrupt semiconductor junctions with respective adjacent regions.

26. The depleted base transistor of claim 24, wherein said insulated gate electrode comprises polycrystalline silicon of P-type conductivity.

27. A depleted base transistor comprising:

a semiconductor substrate having first and second opposing faces;

a cathode contact on the first face;

an anode contact on the second face;

an N-type cathode region in said substrate at the first face, said cathode region forming an ohmic contact with said cathode contact;

a P-type anode region in said substrate at the second face, said anode region forming an ohmic contact with said anode contact;

a trench in said substrate at the first face, said trench having a trench bottom and a trench sidewall extending between the trench bottom and the first face;

an N-type base region of first conductivity type in said substrate, said N-type base region extending between said N-type cathode region and said P-type anode region and forming a non-rectifying junction with said N-type cathode region;

a P-type polycrystalline silicon insulated gate electrode in said trench; and

means, comprising a rectifying junction in said substrate and adjacent the first face, for depleting a portion of said N-type base region of N-type carriers to thereby inhibit traversal of majority carriers from said N-type cathode region to said P-type anode region when said P-type anode region is forward biased relative to said N-type cathode region.

28. The depleted base transistor of claim 27, wherein the rectifying junction is selected from the group consisting of P-N and Schottky junctions.

29. A depleted base transistor comprising:

a monocrystalline silicon carbide substrate having first and second opposing faces;

a cathode contact and an anode contact on the first and second opposing faces of said silicon carbide substrate, respectively;

an N-type silicon carbide cathode region in said silicon carbide substrate, said silicon carbide cathode region forming an ohmic contact with said cathode contact;

an N-type silicon carbide base region in said substrate, between said silicon carbide cathode region and the second face, said silicon carbide base region comprising;

a silicon carbide buffer region adjacent the second face, said silicon carbide buffer region forming an ohmic contact with said anode contact;

a silicon carbide drift region of first conductivity type having a drift region doping concentration and forming a non-rectifying junction with said silicon carbide buffer region;

a silicon carbide blocking voltage enhancement region of first conductivity type extending between said silicon carbide drift region and said silicon carbide cathode region, said silicon carbide blocking voltage enhancement region forming non-rectifying junctions with said silicon carbide cathode region and said silicon carbide drift region and having a blocking voltage enhancement region doping concentration below the drift region doping concentration;

a trench in said substrate at the first face, said trench having a trench bottom which defines an interface between said silicon carbide drift region and an interior of said trench and a trench sidewall which defines an interface between said silicon carbide blocking voltage enhancement region and the interior of said trench;

an insulated gate electrode in the interior of said trench; and

means, comprising a silicon carbide rectifying junction spaced from the trench sidewall and selected from the group consisting of P-N junctions and Schottky junctions, for depleting said silicon carbide blocking voltage enhancement region of majority free carriers to thereby inhibit traversal of majority carriers from said silicon carbide cathode region to said silicon carbide drift region.

30. The depleted base transistor of claim 29, wherein the silicon carbide blocking voltage enhancement region doping concentration is less than about one half times the silicon carbide drift region doping concentration.

31. The depleted base transistor of claim 29, wherein said insulated gate electrode comprises polycrystalline silicon of P-type conductivity.

32. The depleted base transistor of claim 29, wherein the silicon carbide rectifying junction comprises a P-type silicon carbide collector region in said silicon carbide substrate and wherein said silicon carbide collector region forms a P-N junction with said silicon carbide blocking voltage enhancement region and a P-N junction with said silicon carbide cathode region.

33. The depleted base transistor of claim 29, wherein the silicon carbide rectifying junction comprises a metal-filled trench having a bottom which defines an interface between a Schottky barrier metal and said silicon carbide blocking voltage enhancement region.

34. The depleted base transistor of claim 33, wherein the metal work function of the Schottky barrier metal is selected to fully deplete said silicon carbide blocking voltage enhancement region of majority free carriers when said insulated gate electrode, said cathode contact and said anode contact are biased to the same potential.