Series/parallel resonant converter

• US 5,680,301 A
• Filed: 09/02/1992
• Issued: 10/21/1997
• Est. Priority Date: 09/02/1992
• Status: Expired due to Fees

• Current Assignee: Powerware Corporation (Eaton Corporation PLC.)
• Original Assignee: Exide Electronics Corporation (Exide Electronics Group, Inc.)
• Inventors: Widener, Steven, Oughton, George W. Jr.
• Primary Examiner(s): Dougherty, Thomas M.
• Application Number:
  US07/939,441
• Time in Patent Office: 1,875 Days
• Field of Search: 363/17, 363/24-26, 363/97, 363/98, 363/132, 363/137
• US Class Current: 363/132
• CPC Class Codes: H02M 3/01 Resonant DC/DC converters
• CPC Class Codes: H02M 3/33571 Half-bridge at primary side of an isolation transformer
• CPC Class Codes: H02M 7/538 in a push-pull configuration H02M7/5375 takes precedence ; with oscillating arrangements H02M7/53832, H02M7/53846
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
• CPC Class Codes: Y02P 80/10 Efficient use of energy, e.g. using compressed air or pressurized fluid as energy carrier

Abstract

A series/parallel resonant converter includes a resonant control circuit 1 that outputs a pair of alternately high gate drive signals G₁, G₂ ; switches in the form of isolated gate bipolar transistors (IGBTs) Q₁, Q₂ ; diodes D₁, D₂ ; a pair of resonant capacitors C_R ; a series resonant inductor L_RS ; a load 2; a zero current detector 4; a bus 6, 6'"'"'; and a parallel resonant inductor L_RP in parallel with the load. The input line current and voltage are converted into an alternating current I_LOAD and voltage V_LOAD for driving the load 2. The load 2 may include a transformer T₁, half bridge rectifier, capacitor, and PWM inverter.

Claims

1. An electrical circuit for converting a DC bus voltage into an AC current for driving a load, comprising:

(a) first and second transistors (Q₁, Q₂) connected in series such that a collector of the first transistor is connected to a first side of the bus and an emitter of the second transistor is connected to a second side of the bus;

(b) a first diode (D₁) connected between an emitter and the collector of the first transistor and a second diode (D₂) connected between the emitter and a collector of the second transistor;

(c) first and second resonant capacitors (C_R) connected in series such that a first terminal of the first capacitor is connected to the first side of the bus and a second terminal of the second capacitor is connected to the second side of the bus;

(d) a series resonant inductor (L_RS) comprising a first terminal connected to a node between the first and second resonant capacitors and a second terminal adapted to be connected to a first side of the load;

(e) a parallel resonant inductor (L_RP) comprising a first terminal connected to the second terminal of the series resonant inductor and a second terminal connected to a node between the first and second transistors and adapted to be connected to a second side of the load; and

(f) control circuit means for generating first and second gate drive signals (G₁, G₂) for alternately driving the first and second transistors such that an alternating load current (I_LOAD) is provided.

2. The electrical circuit recited in claim 1, further comprising zero current crossing means for detecting when a current (I_R) in the series resonant inductor is zero and controlling the generation of the first and second gate drive signals such that the first gate drive signal is set low when the current is zero and the second gate drive signal is set high following a controlled dead time delay (τ

_D) from the time the first gate drive signal was set low.

3. A series/parallel resonant converter for converting a first DC bus voltage of a first magnitude to a second DC voltage of a second magnitude, comprising:

(a) first and second switches coupled in series such that the first switch is electrically coupled to a first side of the bus and the second switch is electrically coupled to a second side of the bus;

(b) a first diode coupled in parallel with the first switch and a second diode coupled in parallel with the second switch;

(c) first and second resonant capacitors connected in series such that a first terminal of the first capacitor is connected to the first side of the bus and a second terminal of the second capacitor is connected to the second side of the bus;

(d) a series resonant inductor comprising a first terminal connected to a node between the first and second resonant capacitors and a second terminal;

(e) a parallel resonant inductor comprising a first terminal connected to the second terminal of the series resonant inductor and a second terminal connected to a node between the first and second switches;

(f) a transformer comprising a secondary winding and a primary winding, said primary winding comprising a first terminal coupled to the second terminal of the series resonant inductor and a second terminal coupled to the second terminal of the parallel resonant inductor;

(g) a rectifier coupled to the secondary winding; and

(h) control circuit means for generating first and second gate drive signals (G₁, G₂) for alternately driving the first and second switches such that an alternating current (I_LOAD) is provided to the primary winding of the transformer.

4. The series/parallel resonant converter recited in claim 3, further comprising zero current crossing means for detecting when a current (I_R) in the series resonant inductor is zero and controlling the generation of the first and second gate drive signals such that the first gate drive signal is set low when the current is zero and the second gate drive signal is set high following a controlled dead time delay (τ

_D) from the time the first gate drive signal was set low.

5. The series/parallel resonant converter recited in claim 4, wherein said first and second switches comprise members of the following group:

IGBTs, BJTs, FETs, and MCTs.