Method and apparatus for reducing waiting time jitter in pulse stuffing synchronized digital communications

• US 5,680,422 A
• Filed: 04/27/1995
• Issued: 10/21/1997
• Est. Priority Date: 04/27/1995
• Status: Expired due to Term

• Current Assignee: ADTRAN Incorporated (ADTRAN Holdings, Inc.)
• Original Assignee: ADTRAN Incorporated (ADTRAN Holdings, Inc.)
• Inventors: Turner, Michael D., Schneider, Kevin W., Burch, Richard A., Rochell, Timothy D.
• Primary Examiner(s): Bocure, Tesfaldet
• Application Number:
  US08/429,951
• Time in Patent Office: 908 Days
• Field of Search: 375/371, 375/372, 375/363, 375/376, 375/359, 370/102, 370/100.1, 370/101, 370/111, 370/105.3, 327/141, 327/156
• US Class Current: 375/371
• CPC Class Codes: H04J 3/073 Bit stuffing, e.g. PDH

Abstract

A wander reduction mechanism in an HDSL pulse-stuffing synchronization system provides a more precise measure of the phase of the incoming asynchronous signal than is obtained in conventional schemes, in which the only information available is the presence or absence of stuffing pulses. An auxiliary phase comparator and phase adjuster are incorporated into the synchronizer-multiplexer to generate a reference data clock (derived from the synchronized data clock), so that the incoming unsynchronized data clock can be tracked. As the clock is iteratively phase-adjusted, the respective changes are accumulated. At the end of a prescribed measurement interval, the net contents of the accumulator are encoded and transported over the synchronous digital data communication channel to the receiver. By decoding this sequence information, the desynchronizer is able to generate a desynchronized data clock having the same number of net phase adjustments during a measurement period as the reference clock at the synchronizer.

Claims

1. A method for reducing the jitter and wander of a data signal that is passed through a pulse stuffing synchronizer and desynchronizer, said method comprising the steps of:

(a) sequentially adjusting the phase of a reference clock signal so as to cause said reference clock signal to closely track the phase of a clock signal recovered from said data signal;

(b) storing information representative of the net effect of phase adjustments of said reference clock in step (a);

(c) conveying said net effect representative information stored in step (b) to said desynchronizer;

(d) generating a sequence of phase adjustments in accordance with said net effect information; and

(e) generating a clock signal for controlling the operation of said desynchronizer in accordance with said sequence of phase adjustments generated in step (d).

2. A method according to claim 1, wherein step (a) comprises:

(a1) generating said reference clock signal,

(a2) comparing the phase of said reference clock signal with that of said recovered clock signal and generating a phase difference signal representative of whether or not said recovered clock signal leads or lags said reference clock signal, and

(a3) incrementally adjusting the phase of said reference clock signal in accordance with said phase difference signal.

3. A method according to claim 2, wherein step (b) comprises accumulating values of incremental phase adjustments of said reference clock signal over a prescribed measurement interval to derive said net effect of phase adjustments of said reference clock, and storing information representative of said net effect.

4. A method according to claim 3, wherein step (c) comprises encoding said net effect representative information stored in step (b) and conveying said encoded information to said desynchronizer.

5. A method according to claim 4, wherein step (d) comprises decoding said encoded information conveyed to said desynchronizer, and generating therefrom a sequence of phase adjustments, and wherein step (e) comprises:

(e1) generating a clock signal for controlling the operation of said desynchronizer, and

(e2) incrementally adjusting the phase of said clock signal for controlling the operation of said desynchronizer in accordance with said sequence of phase adjustments generated in step (d).

6. A method according to claim 5, wherein step (d) comprises generating said sequence of phase adjustments in accordance with successive results of iteratively performing a prescribed logic operation on said decoded information.

7. A method according to claim 6, wherein said prescribed logic operation produces a ternary output signal having values respectively associated with an incremental increase in, an incremental decrease in, or no change in the phase of said clock signal for controlling the operation of said desynchronizer.

8. A method according to claim 7, wherein said prescribed logic operation produces a ternary output signal having values of -1, 0 or +1.

9. A system for reducing the jitter and wander of a data signal that is passed through a pulse stuffing synchronizer at a transmit site, conveyed over a digital data communication link to a receive site, and recovered by a desynchronizer at said receive site, said system comprising:

at said transmit site,

a timing signal extractor which is operative to recover a clock signal contained in said data signal;

a reference clock generator which generates a reference clock signal;

a phase adjuster which is operative to sequentially adjust the phase of said reference clock signal so as to cause said reference clock signal to track the phase of said clock signal recovered from said data signal;

a phase adjustment accumulator which stores information representative of the net effect of sequential phase adjustments of said reference clock by said phase adjuster; and

a pulse stuffer which is operative to controllably insert into digital data stream to be conveyed over said digital data communication link to said receive site, stuffing pulses and signals containing said information stored by said phase adjustment accumulator.

10. A system according to claim 9, further including, at said receive site,

a stuffing pulse decoder which is operative to derive said net effect representative information signals contained in said digital data stream;

a phase adjustment generator which is operative to generate a sequence of phase adjustments in accordance with said net effect representative information signals; and

a controlled clock signal generator which is operative to generate a clock signal for controlling the operation of said desynchronizer in accordance with said sequence of phase adjustments generated by said phase adjustment generator.

11. A system according to claim 9, wherein, at said transmit site, said phase adjuster includes a phase comparator which is operative to compare the phase of said reference clock signal with that of said recovered clock signal and generates a phase difference signal representative of whether or not said recovered clock signal leads or lags said reference clock signal, and a digitally controlled phase adjuster which incrementally adjusts the phase of said reference clock signal in accordance with said phase difference signal, and thereby cause said reference clock signal to track the phase of said clock signal recovered from said data signal.

12. A system according to claim 9, wherein, at said transmit site, said phase adjustment accumulator is operative to accumulate values of incremental phase adjustments of said reference clock signal over a prescribed measurement interval to derive said net effect of phase adjustments of said reference clock, and stores information representative of said net effect.

13. A system according to claim 12, wherein, at said transmit site, said pulse stuffer is operative to insert into said digital data stream to be conveyed over said digital data communication link to said receive site, encoded information stored by said phase adjustment accumulator.

14. A system according to claim 13, wherein, at said receiver site, said stuffing pulse decoder is operative to decode said encoded information net effect representative information signals contained in said digital data stream, and wherein said phase adjustment generator is operative to generate said sequence of phase adjustments in accordance with the decoded net effect representative information signals.

15. A system according to claim 14, wherein said phase adjustment generator is operative to generate a sequence of phase adjustments in accordance with successive results of iteratively performing a prescribed logic operation on said decoded information.

16. A system according to claim 15, wherein said prescribed logic operation produces a ternary output signal having values respectively associated with an incremental increase in, an incremental decrease in, or no change in the phase of said clock signal for controlling the operation of said desynchronizer.

17. A system according to claim 16, wherein said prescribed logic operation produces a ternary output signal having values of -1, 0 or +1.

18. A method for reducing the jitter and wander of a data signal that is passed through a pulse stuffing synchronizer at a transmit site and transmitted over a digital data communications channel to a desynchronizer at a receive site, said method comprising the steps of:

at said transmit site,

(a) sequentially adjusting the phase of a reference clock signal so as to cause said reference clock signal to closely track the phase of a clock signal recovered from said data signal;

(b) storing information representative of the net effect of phase adjustments of said reference clock in step (a); and

(c) encoding signals representative of said net effect representative information stored in step (b) for transmission to said desynchronizer at said receiver site.

19. A method according to claim 18, further including, at said receive site,

(d) decoding signals representative of said net effect information and generating a sequence of phase adjustments in accordance with said net effect information;

and

(e) generating a clock signal for controlling the operation of said desynchronizer in accordance with said sequence of phase adjustments generated in step (d).

20. A method according to claim 18, wherein step (a) comprises:

(a1) generating a reference clock signal,

(a2) comparing the phase of said reference clock signal with that of said recovered clock signal and generating a phase difference signal representative of whether or not said recovered clock signal leads or lags said reference clock signal, and

(a3) incrementally adjusting the phase of said reference clock signal in accordance with said phase difference signal.

21. A method according to claim 20, wherein step (b) comprises accumulating values of incremental phase adjustments of said reference clock signal over a prescribed measurement interval to derive said net effect of phase adjustments of said reference clock, and storing information representative of said net effect.

22. A method according to claim 21, wherein step (c) comprises encoding said net effect representative information stored in step (b) and conveying said encoded information to said desynchronizer.

23. A method according to claim 22, wherein step (d) comprises decoding said encoded information conveyed to said desynchronizer, and generating therefrom a sequence of phase adjustments, and wherein step (e) comprises:

(e1) generating a clock signal for controlling the operation of said desynchronizer, and

(e2) incrementally adjusting the phase of said clock signal for controlling the operation of said desynchronizer in accordance with said sequence of phase adjustments generated in step (d).

24. A method according to claim 23, wherein step (d) comprises generating said sequence of phase adjustments in accordance with successive results of iteratively performing a prescribed logic operation on said decoded information.

25. A method according to claim 24, wherein said prescribed logic operation produces a ternary output signal having values respectively associated with an incremental increase in, an incremental decrease in, or no change in the phase of said clock signal for controlling the operation of said desynchronizer.

26. A method according to claim 25, wherein said prescribed logic operation produces a ternary output signal having values of -1, 0 or +1.

27. A demultiplexer-desynchronizer arrangement for a receive site of a communication system, said receive site being coupled to receive a digital data stream conveyed over a data communication link from a transmit site, said digital data stream including stuffing pulses that have been inserted at said transmit site and signals containing information representative of the net effect of sequential phase adjustments of a reference clock by a controlled phase adjuster at said transmit site, said arrangement comprising:

a stuffing pulse decoder which is operative to derive said net effect representative information signals contained in said digital data stream;

a phase adjustment generator which is operative to generate a sequence of phase adjustments in accordance with said net effect representative information signals; and

a controlled clock signal generator which is operative to generate a clock signal for controlling the operation of said desynchronizer in accordance with said sequence of phase adjustments generated by said phase adjustment generator.

28. An arrangement according to claim 27, wherein said stuffing pulse decoder is operative to decode said encoded information net effect representative information signals contained in said digital data stream, and wherein said phase adjustment generator is operative to generate said sequence of phase adjustments in accordance with the decoded net effect representative information signals.

29. An arrangement according to claim 28, wherein said phase adjustment generator is operative to generate a sequence of phase adjustments in accordance with successive results of iteratively performing a prescribed logic operation on said decoded information.

30. An arrangement according to claim 29, wherein said prescribed logic operation produces a ternary output signal having values respectively associated with an incremental increase in, an incremental decrease in, or no change in the phase of said clock signal for controlling the operation of said desynchronizer.

31. An arrangement according to claim 30, wherein said prescribed logic operation produces a ternary output signal having values of -1, 0 or +1.