Method and apparatus for synchronizing data in a host memory with data in target MCU memory

• US 5,680,542 A
• Filed: 06/07/1995
• Issued: 10/21/1997
• Est. Priority Date: 06/07/1995
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Gray, Rand, Mulchandani, Deepak
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): Yip, Vincent
• Application Number:
  US08/485,332
• Time in Patent Office: 867 Days
• Field of Search: 395/500, 395/468, 395/471, 395/472, 395/473, 395/200.08, 395/200.19, 395/492, 395/427, 395/183.04, 395/704
• US Class Current: 714/28
• CPC Class Codes: G06F 11/1658 Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit

Abstract

A copy of data in a Host Computer is synchronized with a version located in Shared Memory in a Modular Development System (MDS). Whenever a change in one or more bits in a Line of Data in Shared Memory are detected, a MDS Line Dirty Flag is checked. If the Flag is not set, it is set and a message is sent to the Host Computer that the Line of Data is now dirty. Whenever the Host Computer receives this message for a Line of Data in its visible memory, it sends a request to the MDS to read that Line from Shared Memory and send it to the Host. Otherwise, a Host Line Dirty Flag is set. The Host Computer also sends a request to read a Line of Data when that Line of Data is scrolled onto a screen and the corresponding Host Line Dirty Flag is set.

Claims

1. A method for synchronizing data in a Target Memory with a copy of that data located in a Host Memory on a Host Computer, wherein:

data is organized in the Target Memory in a plurality of Target Data Lines,

each one of the plurality of Target Data Lines comprises a corresponding fixed number of bits,

each one of the plurality of Target Data Lines is uniquely identified by a corresponding Target means for identification,

each of the plurality of Target Data Lines has a corresponding Target Line Dirty Flag,

data is organized in the Host Memory in a plurality of Host Data Lines,

each one of the plurality of Host Data Lines comprises a corresponding fixed number of bits,

each one of the plurality of Host Data Lines is uniquely identified by a corresponding host means for identification,

each of the plurality of Host Data Lines has a corresponding Host Line Dirty Flag,

each of the plurality of Host Data Lines corresponds to a different one of the plurality of Target Data Lines,

said method comprising the steps of;

a) determining whenever one or more bits in one of the plurality of Target Data Lines has been modified, wherein;

the Target Data Line determined to have been modified is a Modified Target Data Line;

b) whenever the Station Controller determines in step (a) that one or more bits of the Target Data Line have been modified, determining whether the corresponding Target Line Dirty Flag is set;

c) whenever the Station Controller determines in step (a) that one or more bits in the Modified Target Data Line have been modified and that the corresponding Target Line Dirty Flag is determined in step (b) not to be set, the following substeps are performed;

1) sending a First Message from the Station Controller to the Host Computer comprising an indication that the Modified Target Data Line has been modified, and

2) setting the Target Line Dirty Flag corresponding to the Modified Target Data Line;

d) whenever a First Message sent in step (c) is received by the Host Computer, setting a Host Line Dirty Flag corresponding to the Modified Target Data Line;

e) sending a Second Message from the Host Computer to the Station Controller indicating the identity of a Host Data Line that has its corresponding Host Line Dirty Flag set;

f) sending a Third Message from the Station Controller to the Host Computer in response to the Second Message received in step (f), wherein said Third Message comprises;

an ordered sequence of bits corresponding to the bits in the Host Data Line requested in the Second Message, and

means for identifying the Host Data Line that corresponds to the ordered sequence of bits in the Third Message;

g) clearing the Target Line Dirty Flag corresponding to the Target Data Line corresponding to the Host Data Line identified by the Third Message sent in step (f);

h) when the Third Message is received by the Host Computer, updating the Host Data Line identified by the Third Message with the ordered sequence of bits in the Third Message; and

i) when the Third Message is received by the Host Computer, clearing the Host Line Dirty Flag corresponding to the Host Data Line identified by the Third Message.

2. The method in claim 1 wherein each of the corresponding fixed number of bits is an integer multiple of sixty-four (64).

3. The method in claim 1 wherein:

the Target Memory is a dual ported memory shared between the Station Controller and a Target Computer.

4. The method in claim 3 wherein within step (a):

the Station Controller determines whether one or more bits in the plurality of Target Data Lines has been modified by comparing the Target Memory with a Secondary Copy of the Target Memory.

5. The method in claim 3 wherein within step (a):

the Station Controller determines whether one or more bits in the plurality of Target Data Lines has been modified by computing a checksum for each of the Target Data Lines and comparing each of the checksums with one or more saved checksums of each of the Target Data Lines saved from a prior checksum computation.

6. The method in claim 1 wherein the First Message, the Second Message, and the Third Message are communicated between the Host computer and the Station Controller over an RS-232 connection.

7. The method in claim 1 wherein the Host Computer delays sending the Second Message for a specified Host Data Line until:

the Host Line Dirty Flag for the Host Data Line is set, and the Host Data Line is in a Visible Memory.

8. A method for real time modification of Target Memory by a Host Computer Debugger executing on a Host Computer with a Host Memory, wherein:

data is organized in the Target Memory in a plurality of Target Data Lines,

each one of the plurality of Target Data Lines comprises a corresponding fixed number of bits,

each one of the plurality of Target Data Lines is uniquely identified by a corresponding Target means for identification,

each of the plurality of Target Data Lines has a corresponding Target Line Dirty Flag,

data is organized in the Host Memory in a plurality of Host Data Lines,

each one of the plurality of Host Data Lines comprises a corresponding fixed number of bits,

each one of the plurality of Host Data Lines is uniquely identified by a corresponding host means for identification,

each of the plurality of Host Data Lines has a corresponding Host Line Dirty Flag,

each of the plurality of Host Data Lines corresponds to a different one of the plurality of Target Data Lines,

said method comprising the steps of;

a) determining whenever one or more bits in one of the plurality of Target Data Lines has been modified, wherein;

the Target Data Line determined to have been modified is a Modified Target Data Line;

b) whenever the Station Controller determines in step (a) that one or more bits of the Target Data Line have been modified, determining whether the corresponding Target Line Dirty Flag is set;

c) whenever the Station Controller determines in step (a) that one or more bits in the Modified Target Data Line have been modified and that the corresponding Target Line Dirty Flag is determined in step (b) not to be set, the following substeps are performed;

1) sending a First Message from the Station Controller to the Host Computer comprising an indication that the Modified Target Data Line has been modified, and

2) setting the Target Line Dirty Flag corresponding to the Modified Target Data Line;

d) whenever a First Message sent in step (c) is received by the Host Computer, setting a Host Line Dirty Flag corresponding to the Modified Target Data Line;

e) sending a Second Message from the Host Computer to the Station Controller indicating the identity of a Host Data Line that has its corresponding Host Line Dirty Flag set, wherein;

the identity of the Host Data Line in the Second Message corresponds to the Modified Target Data Line;

f) sending a Third Message from the Station Controller to the Host Computer in response to the Second Message received in step (f), wherein said Third Message comprises;

an ordered sequence of bits corresponding to the bits in the Host Data Line requested in the Second Message, and

means for identifying the Host Data Line that corresponds to the ordered sequence of bits in the Third Message;

g) clearing the Target Line Dirty Flag corresponding to the Target Data Line corresponding to the Host Data Line identified by the Third Message sent in step (f);

h) when the Third Message is received by the Host Computer, updating the Host Data Line identified by the Third Message with the ordered sequence of bits in the Third Message;

i) when the Third Message is received by the Host Computer, clearing the Host Line Dirty Flag corresponding to the Host Data Line identified by the Third Message;

j) sending a Fourth Message from the Host Computer to the Station Controller that comprises;

means for specifying which bits in the Target Memory are to be modified, and

one or more Replacement Data Bits to replace the corresponding bits in the Target Memory; and

k) when the Fourth Message has been received by the Station Controller, replacing the bits of Target Memory specified in the Fourth Message with the Replacement Data Bits in the Fourth Message.

9. The method in claim 8 which further comprises the step of:

1) when the Third Message has been received by the Host Computer, updating a display of the Target Memory in the Host Computer Debugger with corresponding bits from the ordered sequence of bits from the Third Message.

10. A method for synchronizing data in a Target Memory with a copy of that data located in a Host Memory on a Host Computer, wherein:

data is organized in the Target Memory in a plurality of Target Data Lines,

the Target Memory is a dual ported memory shared between the Station Controller and a Target Computer,

each one of the plurality of Target Data Lines comprises a corresponding fixed number of bits,

each one of the plurality of Target Data Lines is uniquely identified by a corresponding Target means for identification,

each of the plurality of Target Data Lines has a corresponding Target Line Dirty Flag,

data is organized in the Host Memory in a plurality of Host Data Lines,

each one of the plurality of Host Data Lines comprises a corresponding fixed number of bits,

each one of the plurality of Host Data Lines is uniquely identified by a corresponding host means for identification,

each of the plurality of Host Data Lines has a corresponding Host Line Dirty Flag,

each of the plurality of Host Data Lines corresponds to a different one of the plurality of Target Data Lines,

said method comprising the steps of;

a) determining whenever one or more bits in one of the plurality of Target Data Lines has been modified, wherein;

the Target Data Line determined to have been modified is a Modified Target Data Line, and

the Station Controller determines whether one or more bits in the plurality of Target Data Lines has been modified by comparing the Target Memory with a Secondary Copy of the Target Memory;

b) whenever the Station Controller determines in step (a) that one or more bits of the Target Data Line have been modified, determining whether the corresponding Target Line Dirty Flag is set;

c) whenever the Station Controller determines in step (a) that one or more bits in the Modified Target Data Line have been modified and that the corresponding Target Line Dirty Flag is determined in step (b) not to be set, the following substeps are performed;

1) sending a First Message from the Station Controller to the Host Computer comprising an indication that the Modified Target Data Line has been modified, and

2) setting the Target Line Dirty Flag corresponding to the Modified Target Data Line;

d) whenever a First Message sent in step (c) is received by the Host Computer, setting a Host Line Dirty Flag corresponding to the Modified Target Data Line;

e) sending a Second Message from the Host Computer to the Station Controller indicating the identity of a Host Data Line that has its corresponding Host Line Dirty Flag set;

f) sending a Third Message from the Station Controller to the Host Computer in response to the Second Message received in step (f), wherein said Third Message comprises;

an ordered sequence of bits corresponding to the bits in the Host Data Line requested in the Second Message, and

means for identifying the Host Data Line that corresponds to the ordered sequence of bits in the Third Message;

g) clearing the Target Line Dirty Flag corresponding to the Target Data Line corresponding to the Host Data Line identified by the Third Message sent in step (f);

h) when the Third Message is received by the Host Computer, updating the Host Data Line identified by the Third Message with the ordered sequence of bits in the Third Message; and

i) when the Third Message is received by the Host Computer, clearing the Host Line Dirty Flag corresponding to the Host Data Line identified by the Third Message.

11. An apparatus for synchronizing data in a Target Memory with a copy of that data located in a Host Memory on a Host Computer, wherein:

data is organized in the Target Memory in a plurality of Target Data Lines,

each one of the plurality of Target Data Lines comprises a corresponding fixed number of bits,

each one of the plurality of Target Data Lines is uniquely identified by a corresponding Target means for identification,

each of the plurality of Target Data Lines has a corresponding Target Line Dirty Flag,

data is organized in the Host Memory in a plurality of Host Data Lines,

each one of the plurality of Host Data Lines comprises a corresponding fixed number of bits,

each one of the plurality of Host Data Lines is uniquely identified by a corresponding host means for identification,

each of the plurality of Host Data Lines has a corresponding Host Line Dirty Flag,

each of the plurality of Host Data Lines corresponds to a different one of the plurality of Target Data Lines,

said apparatus comprising of;

a) means for determining whenever one or more bits in one of the plurality of Target Data Lines has been modified, wherein;

the Target Data Line determined to have been modified is a Modified Target Data Line;

b) means for determining whether the corresponding Target Line Dirty Flag is set whenever element (a) determines that one or more bits in the Modified Target Data Line have been modified;

c) means for invoking the following subelements whenever element (a) determines that one or more bits in the Modified Target Data Line have been modified and, element (b) determines that the corresponding Target Line Dirty Flag is not set;

1) means for sending a First Message from the Station Controller to the Host Computer comprising an indication that the Modified Target Data Line has been modified, and

2) means for setting the Target Line Dirty Flag corresponding to the Modified Target Data Line;

d) means for setting a Host Line Dirty Flag corresponding to the Modified Target Data Line in response to a receipt of the First Message received by the Host Computer;

e) means for sending a Second Message from the Host Computer to the Station Controller indicating the identity of a Host Data Line that has its corresponding Host Line Dirty Flag set;

f) means for sending a Third Message from the Station Controller to the Host Computer in response to the Second Message received in step (f), wherein said Third Message comprises;

an ordered sequence of bits corresponding to the bits in the Host Data Line requested in the Second Message, and

means for identifying the Host Data Line that corresponds to the ordered sequence of bits in the Third Message;

g) means for clearing the Target Line Dirty Flag corresponding to the Target Data Line corresponding to the Host Data Line identified by the Third Message sent in step (f);

h) means for updating the Host Data Line identified by the Third Message with the ordered sequence of bits in the Third Message in response to a receipt of the Third Message by the Host Computer; and

i) means for clearing the Host Line Dirty Flag corresponding to the Host Data Line identified by the Third Message in response to a receipt of the Third Message by the Host Computer.

12. The apparatus in claim 11 wherein each of the corresponding fixed number of bits is an integer multiple of sixty-four (64).

13. The apparatus in claim 11 wherein:

the Target Memory is a dual ported memory shared between the Station Controller and a Target Computer.

14. The apparatus in claim 13 wherein within element (a):

the means for determining whether one or more bits in the plurality of Target Data Lines has been modified compars the Target Memory with a Secondary Copy of the Target Memory.

15. The apparatus in claim 13 wherein within element (a):

the means for determining whether one or more bits in the plurality of Target Data Lines has been modified computes a checksum for each of the Target Data Lines and compares each of the checksums with one or more saved checksums of each of the Target Data Lines saved from a prior checksum computation.

16. The apparatus in claim 11 wherein the First Message, the Second Message, and the Third Message are communicated between the Host computer and the Station Controller over an RS-232 connection.

17. The apparatus in claim 11 wherein the Host Computer delays sending the Second Message for a specified Host Data Line until:

the Host Line Dirty Flag for the Host Data Line is set, and the Host Data Line is in a Visible Memory.

18. An apparatus for real time modification of Target Memory by a Host Computer Debugger executing on a Host Computer with a Host Memory, wherein:

data is organized in the Target Memory in a plurality of Target Data Lines,

each one of the plurality of Target Data Lines comprises a corresponding fixed number of bits,

each one of the plurality of Target Data Lines is uniquely identified by a corresponding Target means for identification,

each of the plurality of Target Data Lines has a corresponding Target Line Dirty Flag,

data is organized in the Host Memory in a plurality of Host Data Lines,

each one of the plurality of Host Data Lines comprises a corresponding fixed number of bits,

each one of the plurality of Host Data Lines is uniquely identified by a corresponding host means for identification,

each of the plurality of Host Data Lines has a corresponding Host Line Dirty Flag,

each of the plurality of Host Data Lines corresponds to a different one of the plurality of Target Data Lines,

said apparatus comprising of;

a) means for determining whenever one or more bits in one of the plurality of Target Data Lines has been modified, wherein;

the Target Data Line determined to have been modified is a Modified Target Data Line;

b) means for determining whether the corresponding Target Line Dirty Flag is set whenever element (a) determines that one or more bits in the Modified Target Data Line have been modified;

c) means for invoking the following subelements whenever element (a) determines that one or more bits in the Modified Target Data Line have been modified and, element (b) determines that the corresponding Target Line Dirty Flag is not set;

1) means for sending a First Message from the Station Controller to the Host Computer comprising an indication that the Modified Target Data Line has been modified, and

2) means for setting the Target Line Dirty Flag corresponding to the Modified Target Data Line;

d) means for setting a Host Line Dirty Flag corresponding to the Modified Target Data Line in response to a receipt of the First Message received by the Host Computer;

e) means for sending a Second Message from the Host Computer to the Station Controller indicating the identity of a Host Data Line that has its corresponding Host Line Dirty Flag set, wherein;

the identity of the Host Data Line in the Second Message corresponds to the Modified Target Data Line;

f) means for sending a Third Message from the Station Controller to the Host Computer in response to the Second Message received in step (f), wherein said Third Message comprises;

an ordered sequence of bits corresponding to the bits in the Host Data Line requested in the Second Message, and

means for identifying the Host Data Line that corresponds to the ordered sequence of bits in the Third Message;

g) means for clearing the Target Line Dirty Flag corresponding to the Target Data Line corresponding to the Host Data Line identified by the Third Message sent in step (f);

h) means for updating the Host Data Line identified by the Third Message with the ordered sequence of bits in the Third Message in response to a receipt of the Third Message by the Host Computer;

i) means for clearing the Host Line Dirty Flag corresponding to the Host Data Line identified by the Third Message in response to a receipt of the Third Message by the Host Computer;

j) means for sending a Fourth Message from the Host Computer to the Station Controller that comprises;

means for specifying which bits in the Target Memory are to be modified, and

one or more Replacement Data Bits to replace the corresponding bits in the Target Memory; and

k) means for replacing the bits of Target Memory specified in the Fourth Message with the Replacement Data Bits in the Fourth Message in response to the receipt of the Fourth Message by the Station Controller.

19. The apparatus in claim 18 which further comprises:

1) means for updating a display of the Target Memory in the Host Computer Debugger with corresponding bits from the ordered sequence of bits from the Third Message in response to the receipt of the Third Message by the Host Computer.

20. An apparatus for synchronizing data in a Target Memory with a copy of that data located in a Host Memory on a Host Computer, wherein:

data is organized in the Target Memory in a plurality of Target Data Lines,

the Target Memory is a dual ported memory shared between the Station Controller and a Target Computer,

each one of the plurality of Target Data Lines comprises a corresponding fixed number of bits,

each one of the plurality of Target Data Lines is uniquely identified by a corresponding Target means for identification,

each of the plurality of Target Data Lines has a corresponding Target Line Dirty Flag,

data is organized in the Host Memory in a plurality of Host Data Lines,

each one of the plurality of Host Data Lines comprises a corresponding fixed number of bits,

each one of the plurality of Host Data Lines is uniquely identified by a corresponding host means for identification,

each of the plurality of Host Data Lines has a corresponding Host Line Dirty Flag,

each of the plurality of Host Data Lines corresponds to a different one of the plurality of Target Data Lines,

said apparatus comprising;

a) means for determining whenever one or more bits in one of the plurality of Target Data Lines has been modified, wherein;

the Target Data Line determined to have been modified is a Modified Target Data Line, and

Target Data Lines are determined to have been modified by by comparing the Target Memory with a Secondary Copy of the Target Memory;

b) means for determining whether the corresponding Target Line Dirty Flag is set whenever element (a) determines that one or more bits of the Target Data Line have been modified;

c) means for invoking the following elements whenever element (a) determines that one or more bits in the Modified Target Data Line have been modified and element (b) determines that the corresponding Target Line Dirty Flag are not to be set;

1) means for sending a First Message from the Station Controller to the Host Computer comprising an indication that the Modified Target Data Line has been modified, and

2) means for setting the Target Line Dirty Flag corresponding to the Modified Target Data Line;

d) whenever a First Message sent in step (c) is received by the Host Computer, means for setting a Host Line Dirty Flag corresponding to the Modified Target Data Line;

e) means for sending a Second Message from the Host Computer to the Station Controller indicating the identity of a Host Data Line that has its corresponding Host Line Dirty Flag set;

f) means for sending a Third Message from the Station Controller to the Host Computer in response to the Second Message received in step (f), wherein said Third Message comprises;

an ordered sequence of bits corresponding to the bits in the Host Data Line requested in the Second Message, and

means for identifying the Host Data Line that corresponds to the ordered sequence of bits in the Third Message;

g) means for clearing the Target Line Dirty Flag corresponding to the Target Data Line corresponding to the Host Data Line identified by the Third Message sent in step (f);

h) means for updating the Host Data Line identified by the Third Message with the ordered sequence of bits in the Third Message when the Third Message is received by the Host Computer; and

i) means for clearing the Host Line Dirty Flag corresponding to the Host Data Line identified by the Third Message when the Third Message is received by the Host Computer.

21. An apparatus for synchronizing data in a Target Memory with a copy of that data located in a Host Memory on a Host Computer, wherein:

data is organized in the Target Memory in a plurality of Target Data Lines,

each one of the plurality of Target Data Lines comprises a corresponding fixed number of bits,

each one of the plurality of Target Data Lines is uniquely identified by a corresponding Target means for identification,

each of the plurality of Target Data Lines has a corresponding Target Line Dirty Flag,

data is organized in the Host Memory in a plurality of Host Data Lines,

each one of the plurality of Host Data Lines comprises a corresponding fixed number of bits,

each one of the plurality of Host Data Lines is uniquely identified by a corresponding host means for identification,

each of the plurality of Host Data Lines has a corresponding Host Line Dirty Flag,

each of the plurality of Host Data Lines corresponds to a different one of the plurality of Target Data Lines,

said apparatus comprising;

a) a Station Controller connected to the Memory programmed to determine whenever one or more bits in one of the plurality of Target Data Lines has been modified, wherein;

the Target Data Line determined to have been modified is a Modified Target Data Line;

b) the Station Controller programmed to determine whether the corresponding Target Line Dirty Flag is set whenever the Station Controller determines in element (a) that one or more bits of the Target Data Line have been modified;

c) the Station Controller programmed to activate the following elements whenever the Station Controller determines in element (a) that one or more bits in the Modified Target Data Line have been modified and that the corresponding Target Line Dirty Flag is determined in element (b) not to be set;

1) the Station Controller programmed to send a First Message to the Host Computer comprising an indication that the Modified Target Data Line has been modified, and

2) the Station Controller programmed to set the Target Line Dirty Flag corresponding to the Modified Target Data Line;

d) a Host Computer Processor programmed to set a Host Line Dirty Flag corresponding to the Modified Target Data Line whenever a First Message sent in step (c) is received by the Host Computer;

e) the Host Computer Processor programmed to send a Second Message to the Station Controller indicating the identity of a Host Data Line that has its corresponding Host Line Dirty Flag set;

f) the Station Controller programmed to send a Third Message to the Host Computer in response to the Second Message received wherein said Third Message comprises;

an ordered sequence of bits corresponding to the bits in the Host Data Line requested in the Second Message, and

means for identifying the Host Data Line that corresponds to the ordered sequence of bits in the Third Message;

g) the Station Controller programmed to clear the Target Line Dirty Flag corresponding to the Target Data Line corresponding to the Host Data Line identified by the Third Message sent in step (f);

h) the Host Computer Processor programmed to update the Host Data Line identified by the Third Message with the ordered sequence of bits in the Third Message when the Third Message is received by the Host Computer; and

i) the Host Computer Processor programmed to clear the Host Line Dirty Flag corresponding to the Host Data Line identified by the Third Message when the Third Message is received by the Host Computer.