Method and apparatus for built-in self-test with multiple clock circuits

• US 5,680,543 A
• Filed: 10/20/1995
• Issued: 10/21/1997
• Est. Priority Date: 10/20/1995
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Bhawmik, Sudipta
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US08/546,055
• Time in Patent Office: 732 Days
• Field of Search: 395/550, 395/566, 395/183.06, 395/183.08, 395/183.09, 395/183.1, 395/185.08, 371/22.5
• US Class Current: 714/30
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922
• CPC Class Codes: G01R 31/318552 Clock circuits details

Abstract

Built-In Self-Testing of multiple scan chains (12₁ -12_n)can be accomplished by providing separate clock signals (CK₁ -CK_n) that are scheduled by a control circuit (22) so that each chain is clocked at its rated frequency.

Claims

1. A method for supplying clock signals in a Built-In Self-Test circuit containing a plurality of clock regimes C₁, C₂, . . . C_n where n is an integer, each clock regime having an associated one of clock frequency f₁ -f_n, respectively, such that f₁ >

f₂ >

. . . f_n, the method comprising the steps of;

(a) supplying a clock signal CK_i having a frequency f_i (where i is an integer variable that is initially equal to one) to the clock regimes C₁ -C_i while holding the clock regimes C_i+1 -C_n constant; and

(b) successively repeating step (a) after monotonically increasing i by unity one until i=n.

2. The method according to claim 1 wherein each successive clock signal CK_i+1 is synchronized to the clock signal CK_i.

3. The method according to claim 1 wherein each successive clock signal CK_i+1 is staggered from a preceding clock signal CK_i.

4. The method according to claim 1 wherein the BIST circuit contains three clock regimes (n=3) and wherein the clock signals CK₁ CK₂ and CK_n have a frequency of 64 MHz, 32 MHz and 8 MHz, respectively.

5. Apparatus for supplying a plurality of clock regimes C₁, C₂ . . . C_n (where n is an integer) in a Built-In Self-Test circuit with clock signals CK₁ -CK_n having frequencies f₁ -f_n, respectively, such that f₁ >

f₂. . . >

f_n, comprising;

means for generating n separate clock signals CK₁ -CK_n, respectively,

a clock multiplexer circuit for passing a prescribed one of the clock signals CK₁ -CK_n to each of the clock regimes within the Built-In Self-Test circuit;

a control circuit for controlling the clock multiplexer circuit so that the clock regimes C₁ -C_i (where i is an integer variable initially equal to unity) are supplied with the clock signal CK_i while the clock regimes C_i+1 -C_n are held constant as i monotonically increases by unity one until 1=n.

6. The apparatus according to claim 5 wherein the clock multiplexer circuit comprises n multiplexers M₁ -M_n, each multiplexer associated with one of the clock regimes C₁ -C_n, for supplying that regime with a clock signal from the clock generating circuit at a frequency is no higher than a rated clock frequency associated with such clock regime.

7. The apparatus according to claim 6 wherein the control circuit comprises:

a counter for generating a monotonically increasing count having n-1 bits; and

a plurality of logic gates, at least one associated with each multiplexer for controlling that multiplexer in accordance with the count of the counter.