Digital computer for determining a combined tag value from tag values selectively incremented and decremented reflecting the number of messages transmitted and not received

• US 5,680,550 A
• Filed: 02/13/1995
• Issued: 10/21/1997
• Est. Priority Date: 10/03/1990
• Status: Expired due to Fees

• Current Assignee: Thinking Machines Corporation (Oracle Corporation), RTMC Corporation, TM Patents LP
• Original Assignee: TM Patents LP
• Inventors: Kuszmaul, Bradley C., Leiserson, Charles E., Feynman, Carl R., Hillis, W. Daniel, Douglas, David C., Yang, Shaw-Wen
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Chen, Anderson I.
• Application Number:
  US08/388,031
• Time in Patent Office: 981 Days
• Field of Search: 395/200.15, 395/250, 395/375, 395/800, 364/229, 364/230, 364/231.9, 364/242.9, 364/284.3
• US Class Current: 712/11
• CPC Class Codes: G06F 11/08 Error detection or correction by redundancy in data representation, e.g. by using checking codes
• CPC Class Codes: G06F 11/22 Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
• CPC Class Codes: G06F 11/324 Display of status information
• CPC Class Codes: G06F 15/17343 wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture reconfigurable processors arrays G06F15/7867
• CPC Class Codes: G06F 15/17381 Two dimensional, e.g. mesh, torus
• CPC Class Codes: G06F 2201/88 Monitoring involving counting
• CPC Class Codes: H04L 45/48 Routing tree calculation
• CPC Class Codes: H04L 49/35 Switches specially adapted for specific applications
• CPC Class Codes: H04L 49/555 Error detection

Abstract

A digital computer includes a plurality of processing elements, a command processor, a diagnostic processor and a communications network. The processing elements each performs data processing and data communications operations in connection with commands. The processing elements also performing diagnostic operations in response to diagnostic operation requests and providing diagnostic results in response thereto. The command processor generates commands for the processing elements, and also performs diagnostic operations in response to diagnostic operation requests and providing diagnostic results in response thereto. The diagnostic processor generates diagnostic requests. The communication network includes three elements, including a data router, a control network and a diagnostic network. The data router is connected to the processing elements for facilitating the transfer of data among them during a data communications operation. The control network is connected to the processing elements and the command processor for transferring commands from the command processor to the processing elements. The diagnostic network connected to the processing elements, the command processor and the diagnostic processor for transferring diagnostic requests from the diagnostic processor to the processing elements and the command processor and for transferring diagnostic results from the processing elements and the command processor to the diagnostic processor.

Claims

1. A digital computer comprising:

a plurality of message generating nodes interconnected by a routing network;

A. said routing network for transferring messages among said message generating elements;

B. each message generating node including;

i. a message processing element for generating messages, each message including a tag field containing a tag value for transmission over said routing network, and for receiving messages from said routing network; and

ii. a message counter whose contents are selectively incremented and decrement in response to the tag value of the tag field of transmitted and received; and

C. a combine network for performing a combine operation in connection with the lag values of the message counters of said message generating nodes to determine a combined tag value reflecting the number of messages which have been transmitted by said message generating nodes over the routing network which have not been received by said message generating nodes.

2. A digital computer as defined in claim 1 in which the routing network comprises a plurality of router nodes interconnected in a tree pattern in a series of levels from a leaf level to a root level, the message generating nodes being connected to transmit messages to and receive messages from router nodes at the leaf level.

3. A digital computer as defined in claim 1 in which said message counter includes:

A. a counter for generating a digital value in response to a current value, a count increment enable signal which enables said counter to increment, and a count decrement enable signal which enables said counter to decrement;

B. an increment enable signal generator for selectively generating said count increment enable signal in response to (i) the tag value of the tag field of a message generated by the message processing element for transmission over the routing network, and (ii) a count mask; and

C. a decrement enable signal generator for selectively generating said count decrement enable signal in response to (i) the tag value of the tag field of a message received by the message processing element from said routing network, and (ii) said count mask.

4. A digital computer as defined in claim 3 in which said count mask comprises a plurality of count mask bits each having selected conditions, said increment enable signal generator comprising:

A. increment selection means for receiving a plurality of count mask signals each representative of the condition of a count mask bit, said increment selection means being responsive to the tag value of the tag field of a message generated by the message processing element for transmission over the routing network to selectively couple one of the count mask signals as an increment enable signal; and

B. increment gate means for generating said count increment enable signal in response to said increment enable signal and a signal indicating transmission of a message generated by the message processing element over the routing network.

5. A digital computer as defined in claim 4 in which message generating elements of at least some of said message generating nodes include a plurality of ports for concurrently generating a plurality of messages for transmission over said routing network, said message counter including:

A. a plurality of increment enable signal generators each associated with one of said ports for generating a port increment enable signal; and

B. a count increment enable consolidation circuit for generating said count increment enable signal in response to the port increment enable signals of all of said increment enable signal generators.

6. A digital computer as defined by claim 4 in which said count mask comprises a plurality of count mask bits each having selected conditions, said decrement enable signal generator comprising:

A. decrement selection means for receiving a plurality of count mask signals each representative of the condition of a count mask bit, said decrement selection means being responsive to the tag value of the tag field of a message received by the message processing element over the routing network to selectively couple one of the count mask signals as a decrement enable signal; and

B. decrement gate means for generating said count increment enable signal in response to said decrement enable signal and a signal indicating receipt of a message by the message processing element over the routing network.

7. A digital computer as defined in claim 6 in which message generating elements of at least some of said message generating nodes include a plurality of ports for concurrently receiving a plurality of messages from said routing network, said message counter including:

A. a plurality of decrement enable signal generators each associated with one of said ports for generating a port decrement enable signal, the decrement gate means of the decrement enable signal generator associated with least one of said ports generating the port decrement enable signal in response to a selectively buffered message reception signal;

B. a selective buffer circuit for generating said selectively buffered message reception signal in response to port message reception signals from said ports, each port message reception signal indicating reception by an associated port of a message from said network; and

C. a count decrement enable consolidation circuit for generating said count decrement enable signal in response to the port decrement enable signals of all of said decrement enable signal generators.

8. A digital computer as defined in claim 7 in which said selective buffer circuit includes:

A. immediate coincidence means for generating an unbuffered message reception signal in response to a port message reception signal from the port assoicated with the selective buffer circuit indicating receipt of a message thereby, in the absence the port message reception signals from the other ports indicating concurrent receipt of messages thereby;

B. buffer means for generating a delayed buffered message reception signal in response to a port message reception signal from the port assoicated with the selective buffer circuit indicating receipt of a message thereby, in the presence of the port message reception signals from the other ports indicating concurrent receipt of messages thereby; and

C. means for generating said selectively buffered message reception signal in response to said unbuffered message reception signal and said delayed buffered message reception signal.

9. A digital computer as defined in claim 1 in which said message processing element further includes means for generating an initial count value, said message counter including:

A. a register for storing a current count value;

B. count modification means for receiving said current count value from said register and selectively generating an updated count value representing an incremented count value in response to transmission of a message by said message generating element or a decremented count value in response to reception of a message by said message generating element; and

C. count selection means for selectively coupling said initial count value or said updated count value to said register for storage as the current count value.

10. A digital computer as defined in claim 9 in which said register stores said updated count value in response to a load enable signal generated by a load enable control circuit in response to transmission of a message by said message generating element or reception of a message by said message generating element, or in response to receipt of an initial count load enable signal received from said message generating element concurrently with an initial count value.

11. A digital computer as defined in claim 10 in which said load enable control circuit disables generation of said load enable signal in response to contemporaneous transmission of a message by said message generating element and reception of a message by said message generating element.

12. A digital computer as defined in claim 1 in which said message counter includes:

A. a counter for generating a digital value in response to a current value, a count increment enable signal which enables said counter to increment, and a count decrement enable signal which enables said counter to decrement;

B. an increment enable signal generator for selectively generating said count increment enable signal in response to transmission of a message generated by the message processing element over the routing network; and

C. a decrement enable signal generator for selectively generating said count decrement enable signal in response to reception of a message received by the message processing element from said routing network.

13. A digital computer as defined in claim 12 in which message generating elements of at least some of said message generating nodes include a plurality of ports for concurrently generating a plurality of messages for transmission over said routing network, said message counter including:

A. a plurality of increment enable signal generators each associated with one of said ports for generating a port increment enable signal; and

B. a count increment enable consolidation circuit for generating said count increment enable signal in response to the port increment enable signals of all of said increment enable signal generators.

14. A digital computer as defined in claim 12 in which message generating elements of at least some of said message generating nodes include a plurality of ports for concurrently receiving a plurality of messages from said routing network, said message counter including:

A. a plurality of decrement enable signal generators each associated with one of said ports for generating a port decrement enable signal, the decrement gate means of the decrement enable signal generator associated with at least one of said ports generating the port decrement enable signal in response to a selectively buffered message reception signal;

B. a selective buffer circuit for generating said selectively buffered message reception signal in response to port message reception signals from said ports, each port message reception signal indicating reception by an associated port of a message from said network;

C. a count decrement enable consolidation circuit for generating said count decrement enable signal in response to the port decrement enable signals of all of said decrement enable signal generators.

15. A digital computer as defined in claim 14 in which said selective buffer circuit includes:

A. immediate coincidence means for generating an unbuffered message reception signal in response to a port message reception signal from the port assoicated with the selective buffer circuit indicating receipt of a message thereby, in the absence the port message reception signals from the other ports indicating concurrent receipt of messages thereby;

B. buffer means for generating a delayed buffered message reception signal in response to a port message reception signal from the port assoicated with the selective buffer circuit indicating receipt of a message thereby, in the presence of the port message reception signals from the other ports indicating concurrent receipt of messages thereby; and

C. means for generating said selectively buffered message reception signal in response to said unbuffered message reception signal and said delayed buffered message reception signal.

16. A digital computer as defined in claim 1 further comprising means for controlling operations by said message generating nodes in response to the combined count value generated by said combine network.